273 lines
9.2 KiB
Verilog
273 lines
9.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adc_decimate(
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input adc_clk,
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input [15:0] adc_data_a,
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input [15:0] adc_data_b,
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input adc_valid_a,
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input adc_valid_b,
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output reg [15:0] adc_dec_data_a,
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output reg [15:0] adc_dec_data_b,
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output reg adc_dec_valid_a,
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output reg adc_dec_valid_b,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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input [ 2:0] s_axi_awprot,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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input [ 2:0] s_axi_arprot,
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output s_axi_arready,
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output s_axi_rvalid,
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output [31:0] s_axi_rdata,
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output [ 1:0] s_axi_rresp,
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input s_axi_rready);
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// internal signals
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wire up_clk;
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wire up_rstn;
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wire [13:0] up_waddr;
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wire [31:0] up_wdata;
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wire up_wack;
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wire up_wreq;
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wire up_rack;
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wire [31:0] up_rdata;
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wire up_rreq;
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wire [13:0] up_raddr;
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wire [31:0] decimation_ratio;
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wire [31:0] filter_mask;
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wire [105:0] adc_cic_data_a;
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wire adc_cic_valid_a;
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wire [105:0] adc_cic_data_b;
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wire adc_cic_valid_b;
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wire [25:0] adc_fir_data_a;
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wire adc_fir_valid_a;
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wire [25:0] adc_fir_data_b;
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wire adc_fir_valid_b;
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reg adc_dec_valid_a_filter;
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reg adc_dec_valid_b_filter;
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reg [31:0] decimation_counter;
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reg [15:0] decim_rate_cic;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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cic_decim cic_decimation_a (
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.clk(adc_clk),
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.clk_enable(adc_valid_a),
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.reset(adc_rst),
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.filter_in(adc_data_a[11:0]),
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.rate(decim_rate_cic),
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.load_rate(1'b0),
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.filter_out(adc_cic_data_a),
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.ce_out(adc_cic_valid_a));
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cic_decim cic_decimation_b (
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.clk(adc_clk),
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.clk_enable(adc_valid_b),
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.reset(adc_rst),
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.filter_in(adc_data_b[11:0]),
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.rate(decim_rate_cic),
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.load_rate(1'b0),
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.filter_out(adc_cic_data_b),
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.ce_out(adc_cic_valid_b));
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fir_decim fir_decimation_a (
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.clk(adc_clk),
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.clk_enable(adc_cic_valid_a),
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.reset(adc_rst),
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.filter_in(adc_cic_data_a[11:0]),
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.filter_out(adc_fir_data_a),
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.ce_out(adc_fir_valid_a));
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fir_decim fir_decimation_b (
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.clk(adc_clk),
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.clk_enable(adc_cic_valid_b),
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.reset(adc_rst),
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.filter_in(adc_cic_data_b[11:0]),
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.filter_out(adc_fir_data_b),
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.ce_out(adc_fir_valid_b));
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always @(*) begin
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case (filter_mask)
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16'h1: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h2: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h3: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h6: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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16'h7: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]};
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default: adc_dec_data_a = adc_data_a;
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endcase
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case (filter_mask)
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16'h1: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h2: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h3: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h6: adc_dec_valid_a_filter = adc_fir_valid_a;
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16'h7: adc_dec_valid_a_filter = adc_fir_valid_a;
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default: adc_dec_valid_a_filter = adc_valid_a;
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endcase
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case (filter_mask)
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16'h1: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h2: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h3: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h6: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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16'h7: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]};
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default: adc_dec_data_b = adc_data_b;
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endcase
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case (filter_mask)
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16'h1: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h2: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h3: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h6: adc_dec_valid_b_filter = adc_fir_valid_b;
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16'h7: adc_dec_valid_b_filter = adc_fir_valid_b;
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default: adc_dec_valid_b_filter = adc_valid_b;
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endcase
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case (filter_mask)
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16'h1: decim_rate_cic = 16'd5;
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16'h2: decim_rate_cic = 16'd50;
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16'h3: decim_rate_cic = 16'd500;
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16'h6: decim_rate_cic = 16'd5000;
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16'h7: decim_rate_cic = 16'd50000;
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default: decim_rate_cic = 16'd1;
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endcase
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end
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always @(posedge adc_clk) begin
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if (adc_rst == 1'b1) begin
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decimation_counter <= 32'b0;
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adc_dec_valid_a <= 1'b0;
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adc_dec_valid_b <= 1'b0;
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end else begin
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if (adc_dec_valid_a_filter == 1'b1) begin
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if (decimation_counter < decimation_ratio) begin
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decimation_counter <= decimation_counter + 1;
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adc_dec_valid_a <= 1'b0;
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adc_dec_valid_b <= 1'b0;
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end else begin
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decimation_counter <= 0;
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adc_dec_valid_a <= 1'b1;
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adc_dec_valid_b <= 1'b1;
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end
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end else begin
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adc_dec_valid_a <= 1'b0;
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adc_dec_valid_b <= 1'b0;
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end
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end
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end
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axi_adc_decimate_reg axi_adc_decimate_reg (
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.clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_decimation_ratio (decimation_ratio),
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.adc_filter_mask (filter_mask),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq),
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.up_waddr (up_waddr),
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.up_wdata (up_wdata),
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.up_wack (up_wack),
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.up_rreq (up_rreq),
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.up_raddr (up_raddr),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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