Istvan Csomortani 03bec4b49c ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location ... In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to receive a device clock properly we have to use pin which is connected to a global clock buffer. Luckily SYSREF is connected to global clock pin; swap to port to receive the device clock correctly. Also, swap the ports in both ZC706 and A10SOC carriers.		2019-10-17 09:59:23 +03:00
..
ad40xx_fmc	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
ad738x_fmc	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
ad5758_sdz	system_id: deployed ip	2019-08-06 16:53:11 +03:00
ad5766_sdz	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
ad6676evb	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
ad7134_fmc	ad7134: Change maximum data width from 24b to 32b	2019-10-16 17:35:24 +03:00
ad7405_fmc	system_id: deployed ip	2019-08-06 16:53:11 +03:00
ad7616_sdz	system_id: deployed ip	2019-08-06 16:53:11 +03:00
ad7768evb	system_id: deployed ip	2019-08-06 16:53:11 +03:00
ad9208_dual_ebz	ad9208_dual_ebz: Cleanup workarounds	2019-09-16 10:00:14 +03:00
ad9265_fmc	system_id: deployed ip	2019-08-06 16:53:11 +03:00
ad9434_fmc	system_id: deployed ip	2019-08-06 16:53:11 +03:00
ad9467_fmc	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
ad9739a_fmc	system_id: deployed ip	2019-08-06 16:53:11 +03:00
ad77681evb	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
ad_fmclidar1_ebz	ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location	2019-10-17 09:59:23 +03:00
adaq7980_sdz	adaq7980: Software configurable trigger	2019-09-27 17:02:52 +03:00
adrv9009	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
adrv9009_zu11eg_som	adrv9009_zu11eg_som: i2s mclk fix	2019-10-03 17:30:57 +03:00
adrv9361z7035	adrv9361z7035/common/ccbox_constr.xdc: Cosmetics only	2019-07-17 10:37:30 +03:00
adrv9364z7020	util_clkdiv: Seperate the IP source into an intel and xilinx version	2019-06-29 06:53:51 +03:00
adrv9371x	adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters	2019-10-08 10:38:46 +03:00
adv7511	system_id: deployed ip	2019-08-06 16:53:11 +03:00
arradio	project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl	2019-06-29 06:53:51 +03:00
cn0363	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
cn0506_rgmii	cn0506_rgmii/zcu102: Fix README typo	2019-09-26 16:33:45 +03:00
common	a10soc_system_qsys: sys_dma_clk clock_source inherit its clock frequency from its source	2019-10-02 15:32:17 +03:00
dac_fmc_ebz	dac_fmc_ebz: Add project info to sys_id	2019-10-15 17:08:53 +03:00
daq2	adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters	2019-10-08 10:38:46 +03:00
daq3	adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters	2019-10-08 10:38:46 +03:00
fmcadc2	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
fmcadc5	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
fmcjesdadc1	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
fmcomms2	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
fmcomms5	fmcomms5: remove clock skew handling	2019-09-27 17:52:10 +03:00
fmcomms11	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
imageon	Makefile: Update makefiles	2019-08-26 16:58:01 +03:00
m2k	m2k: Change constraint to match the new LA path	2019-09-13 11:55:11 +03:00
pluto	zynq:all: fix SPI clock constraint	2019-08-09 16:39:56 +03:00
scripts	adi_project_intel: Enable HPS internal timing	2019-10-02 15:32:17 +03:00
sidekiqz2	project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl	2019-06-29 06:53:51 +03:00
usrpe31x	project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl	2019-06-29 06:53:51 +03:00
Makefile	Regenerate project top-level Makefiles	2018-04-11 15:09:54 +03:00