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Istvan Csomortani 0007054638 ad9625x2_fmc: Add a separate SPI for the DAC interface 
DAC spi interface is controlled by an axi_spi core.
Modifications on GPIO layout: pwr_good is 12, vdither 13 and trig is 14.
 		2014-12-02 19:29:18 +02:00
library up_axi: Fix up_raddr/up_waddr port width 2014-12-01 13:22:28 +01:00
projects ad9625x2_fmc: Add a separate SPI for the DAC interface 2014-12-02 19:29:18 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga