// *************************************************************************** // *************************************************************************** // Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are // developed independently, and may be accompanied by separate and unique license // terms. // // The user should read each of these license terms, and understand the // freedoms and responsibilities that he or she has by using this source/core. // // This core is distributed in the hope that it will be useful, but WITHOUT ANY // WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR // A PARTICULAR PURPOSE. // // Redistribution and use of source or resulting binaries, with or without modification // of this file, are permitted under one of the following two license terms: // // 1. The GNU General Public License version 2 as published by the // Free Software Foundation, which can be found in the top level directory // of this repository (LICENSE_GPL2), and also online at: // // // OR // // 2. An ADI specific BSD license, which can be found in the top level directory // of this repository (LICENSE_ADIBSD), and also on-line at: // https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD // This will allow to generate bit files and not release the source code, // as long as it attaches to an ADI device. // // *************************************************************************** // *************************************************************************** `timescale 1ns/100ps module system_top #( parameter TX_JESD_L = 8, parameter TX_NUM_LINKS = 1, parameter RX_JESD_L = 8, parameter RX_NUM_LINKS = 1, parameter JESD_MODE = "8B10B" ) ( input sys_rst, input sys_clk_p, input sys_clk_n, input uart_sin, output uart_sout, output ddr4_act_n, output [16:0] ddr4_addr, output [ 1:0] ddr4_ba, output [ 0:0] ddr4_bg, output ddr4_ck_p, output ddr4_ck_n, output [ 0:0] ddr4_cke, output [ 1:0] ddr4_cs_n, inout [ 8:0] ddr4_dm_n, inout [71:0] ddr4_dq, inout [ 8:0] ddr4_dqs_p, inout [ 8:0] ddr4_dqs_n, output [ 0:0] ddr4_odt, output ddr4_reset_n, output mdio_mdc, inout mdio_mdio, input phy_clk_p, input phy_clk_n, input phy_rx_p, input phy_rx_n, output phy_tx_p, output phy_tx_n, input phy_dummy_port_in, inout [7:0] gpio_bd, inout iic_scl, inout iic_sda, input vadj_1v8_pgood, // FMC HPC IOs input [1:0] agc0, input [1:0] agc1, input [1:0] agc2, input [1:0] agc3, input clkin8_n, input clkin8_p, input clkin6_n, input clkin6_p, input fpga_refclk_in_n, input fpga_refclk_in_p, input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, input fpga_syncin_0_n, input fpga_syncin_0_p, inout fpga_syncin_1_n, inout fpga_syncin_1_p, output fpga_syncout_0_n, output fpga_syncout_0_p, inout fpga_syncout_1_n, inout fpga_syncout_1_p, inout [10:0] gpio, inout hmc_gpio1, output hmc_sync, input [1:0] irqb, output rstb, output [1:0] rxen, output spi0_csb, input spi0_miso, output spi0_mosi, output spi0_sclk, output spi1_csb, output spi1_sclk, inout spi1_sdio, input sysref2_n, input sysref2_p, output [1:0] txen ); // internal signals wire [63:0] gpio_i; wire [63:0] gpio_o; wire [63:0] gpio_t; wire [ 7:0] spi_csn; wire spi_mosi; wire spi_miso; wire spi1_miso; wire ref_clk; wire sysref; wire [TX_NUM_LINKS-1:0] tx_syncin; wire [RX_NUM_LINKS-1:0] rx_syncout; wire [7:0] tx_data_p_loc; wire [7:0] tx_data_n_loc; wire clkin6; wire clkin8; wire tx_device_clk; wire rx_device_clk; // instantiations IBUFDS_GTE4 i_ibufds_ref_clk ( .CEB (1'd0), .I (fpga_refclk_in_p), .IB (fpga_refclk_in_n), .O (ref_clk), .ODIV2 ()); IBUFDS i_ibufds_sysref ( .I (sysref2_p), .IB (sysref2_n), .O (sysref)); IBUFDS i_ibufds_device_clk ( .I (clkin6_p), .IB (clkin6_n), .O (clkin6)); IBUFDS_GTE4 i_ibufds_rx_device_clk ( .I (clkin8_p), .IB (clkin8_n), .CEB(1'b0), .ODIV2 (clkin8)); IBUFDS i_ibufds_syncin_0 ( .I (fpga_syncin_0_p), .IB (fpga_syncin_0_n), .O (tx_syncin[0])); OBUFDS i_obufds_syncout_0 ( .I (rx_syncout[0]), .O (fpga_syncout_0_p), .OB (fpga_syncout_0_n)); BUFG i_tx_device_clk ( .I (clkin6), .O (tx_device_clk) ); BUFG_GT i_rx_device_clk ( .I (clkin8), .O (rx_device_clk) ); // spi assign spi0_csb = spi_csn[0]; assign spi0_mosi = spi_mosi; assign spi0_sclk = spi_clk; assign spi1_csb = spi_csn[1]; assign spi1_sclk = spi_clk; assign spi_miso = ~spi_csn[0] ? spi0_miso : ~spi_csn[1] ? spi1_miso : 1'b0; ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi ( .spi_csn (spi_csn[1]), .spi_clk (spi_clk), .spi_mosi (spi_mosi), .spi_miso (spi1_miso), .spi_sdio (spi1_sdio), .spi_dir ()); // gpios ad_iobuf #(.DATA_WIDTH(12)) i_iobuf ( .dio_t (gpio_t[43:32]), .dio_i (gpio_o[43:32]), .dio_o (gpio_i[43:32]), .dio_p ({hmc_gpio1, // 43 gpio[10:0]})); // 42-32 assign gpio_i[44] = agc0[0]; assign gpio_i[45] = agc0[1]; assign gpio_i[46] = agc1[0]; assign gpio_i[47] = agc1[1]; assign gpio_i[48] = agc2[0]; assign gpio_i[49] = agc2[1]; assign gpio_i[50] = agc3[0]; assign gpio_i[51] = agc3[1]; assign gpio_i[52] = irqb[0]; assign gpio_i[53] = irqb[1]; assign hmc_sync = gpio_o[54]; assign rstb = gpio_o[55]; assign rxen[0] = gpio_o[56]; assign rxen[1] = gpio_o[57]; assign txen[0] = gpio_o[58]; assign txen[1] = gpio_o[59]; generate if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin assign tx_syncin[1] = fpga_syncin_1_p; end else begin ad_iobuf #(.DATA_WIDTH(2)) i_syncin_iobuf ( .dio_t (gpio_t[61:60]), .dio_i (gpio_o[61:60]), .dio_o (gpio_i[61:60]), .dio_p ({fpga_syncin_1_n, // 61 fpga_syncin_1_p})); // 60 end if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin assign fpga_syncout_1_p = rx_syncout[1]; assign fpga_syncout_1_n = 0; end else begin ad_iobuf #(.DATA_WIDTH(2)) i_syncout_iobuf ( .dio_t (gpio_t[63:62]), .dio_i (gpio_o[63:62]), .dio_o (gpio_i[63:62]), .dio_p ({fpga_syncout_1_n, // 63 fpga_syncout_1_p})); // 62 end endgenerate ad_iobuf #(.DATA_WIDTH(8)) i_iobuf_bd ( .dio_t (gpio_t[7:0]), .dio_i (gpio_o[7:0]), .dio_o (gpio_i[7:0]), .dio_p (gpio_bd)); assign gpio_i[59:54] = gpio_o[59:54]; assign gpio_i[31:8] = gpio_o[31:8]; system_wrapper i_system_wrapper ( .sys_rst (sys_rst), .sys_clk_clk_n (sys_clk_n), .sys_clk_clk_p (sys_clk_p), .ddr4_act_n (ddr4_act_n), .ddr4_adr (ddr4_addr), .ddr4_ba (ddr4_ba), .ddr4_bg (ddr4_bg), .ddr4_ck_c (ddr4_ck_n), .ddr4_ck_t (ddr4_ck_p), .ddr4_cke (ddr4_cke), .ddr4_cs_n (ddr4_cs_n), .ddr4_dm_n (ddr4_dm_n), .ddr4_dq (ddr4_dq), .ddr4_dqs_c (ddr4_dqs_n), .ddr4_dqs_t (ddr4_dqs_p), .ddr4_odt (ddr4_odt), .ddr4_reset_n (ddr4_reset_n), .phy_sd (1'b1), .phy_dummy_port_in (phy_dummy_port_in), .sgmii_rxn (phy_rx_n), .sgmii_rxp (phy_rx_p), .sgmii_txn (phy_tx_n), .sgmii_txp (phy_tx_p), .mdio_mdc (mdio_mdc), .mdio_mdio_io (mdio_mdio), .sgmii_phyclk_clk_n (phy_clk_n), .sgmii_phyclk_clk_p (phy_clk_p), .iic_main_scl_io (iic_scl), .iic_main_sda_io (iic_sda), .uart_sin (uart_sin), .uart_sout (uart_sout), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), .spi_csn_i (spi_csn), .spi_csn_o (spi_csn), .spi_sdi_i (spi_miso), .spi_sdo_i (spi_mosi), .spi_sdo_o (spi_mosi), .gpio0_i (gpio_i[31:0]), .gpio0_o (gpio_o[31:0]), .gpio0_t (gpio_t[31:0]), .gpio1_i (gpio_i[63:32]), .gpio1_o (gpio_o[63:32]), .gpio1_t (gpio_t[63:32]), // FMC HPC .rx_data_0_n (rx_data_n[0]), .rx_data_0_p (rx_data_p[0]), .rx_data_1_n (rx_data_n[1]), .rx_data_1_p (rx_data_p[1]), .rx_data_2_n (rx_data_n[2]), .rx_data_2_p (rx_data_p[2]), .rx_data_3_n (rx_data_n[3]), .rx_data_3_p (rx_data_p[3]), .rx_data_4_n (rx_data_n[4]), .rx_data_4_p (rx_data_p[4]), .rx_data_5_n (rx_data_n[5]), .rx_data_5_p (rx_data_p[5]), .rx_data_6_n (rx_data_n[6]), .rx_data_6_p (rx_data_p[6]), .rx_data_7_n (rx_data_n[7]), .rx_data_7_p (rx_data_p[7]), .tx_data_0_n (tx_data_n_loc[0]), .tx_data_0_p (tx_data_p_loc[0]), .tx_data_1_n (tx_data_n_loc[1]), .tx_data_1_p (tx_data_p_loc[1]), .tx_data_2_n (tx_data_n_loc[2]), .tx_data_2_p (tx_data_p_loc[2]), .tx_data_3_n (tx_data_n_loc[3]), .tx_data_3_p (tx_data_p_loc[3]), .tx_data_4_n (tx_data_n_loc[4]), .tx_data_4_p (tx_data_p_loc[4]), .tx_data_5_n (tx_data_n_loc[5]), .tx_data_5_p (tx_data_p_loc[5]), .tx_data_6_n (tx_data_n_loc[6]), .tx_data_6_p (tx_data_p_loc[6]), .tx_data_7_n (tx_data_n_loc[7]), .tx_data_7_p (tx_data_p_loc[7]), .ref_clk_q0 (ref_clk), .ref_clk_q1 (ref_clk), .rx_device_clk (rx_device_clk), .tx_device_clk (tx_device_clk), .rx_sync_0 (rx_syncout), .tx_sync_0 (tx_syncin), .rx_sysref_0 (sysref), .tx_sysref_0 (sysref) ); assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0]; endmodule // *************************************************************************** // ***************************************************************************