####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

PROJECT_NAME := adrv9364z7020_ccbob_lvds

M_DEPS += ../common/ccbob_constr.xdc
M_DEPS += ../common/ccbob_bd.tcl
M_DEPS += ../common/adrv9364z7020_constr_lvds.xdc
M_DEPS += ../common/adrv9364z7020_constr.xdc
M_DEPS += ../common/adrv9364z7020_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/axi_ad9361/axi_ad9361_delay.tcl

LIB_DEPS += axi_ad9361
LIB_DEPS += axi_dmac
LIB_DEPS += axi_gpreg
LIB_DEPS += axi_sysid
LIB_DEPS += sysid_rom
LIB_DEPS += util_pack/util_cpack2
LIB_DEPS += util_pack/util_upack2
LIB_DEPS += util_rfifo
LIB_DEPS += util_tdd_sync
LIB_DEPS += util_wfifo
LIB_DEPS += xilinx/util_clkdiv

include ../../scripts/project-xilinx.mk