analog.com user ip_pid_controller 1.0 clk CLK clk rst DATA rst LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}} ref_speed DATA ref_speed LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} new_motor_speed DATA new_motor_speed LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}}}} motor_speed DATA motor_speed LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} kp DATA kp LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} ki DATA ki LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} kd DATA kd LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} err DATA err LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} pwm DATA pwm LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} speed DATA speed LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 32} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 16} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}} xilinx_verilogsynthesis Verilog Synthesis verilogSource:vivado.xilinx.com:synthesis verilog ip_pid_controller xilinx_verilogsynthesis_view_fileset xilinx_verilogbehavioralsimulation Verilog Simulation verilogSource:vivado.xilinx.com:simulation verilog ip_pid_controller xilinx_verilogbehavioralsimulation_view_fileset xilinx_xpgui UI Layout :vivado.xilinx.com:xgui.ui xilinx_xpgui_view_fileset xilinx_utilityxitfiles Utility XIT/TTCL :vivado.xilinx.com:xit.util xilinx_utilityxitfiles_view_fileset clk in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation rst in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ref_speed in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation new_motor_speed in std_logic xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation motor_speed in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation kp in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation ki in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation kd in 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation err out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation pwm out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation speed out 31 0 std_logic_vector xilinx_verilogsynthesis xilinx_verilogbehavioralsimulation xilinx_verilogsynthesis_view_fileset ip_pid_controller_c_addsub_v12_0_0/ip_pid_controller_c_addsub_v12_0_0.xci xci ip_pid_controller_c_addsub_v12_0_1/ip_pid_controller_c_addsub_v12_0_1.xci xci ip_pid_controller_mult_gen_v12_0_0/ip_pid_controller_mult_gen_v12_0_0.xci xci ip_pid_controller_div_gen_v5_1_0/ip_pid_controller_div_gen_v5_1_0.xci xci ip_pid_controller_c_counter_binary_v12_0_0/ip_pid_controller_c_counter_binary_v12_0_0.xci xci constrs/ip_pid_controller.xdc xdc hdl/conv_pkg.v verilogSource true work hdl/synth_reg.v verilogSource work hdl/synth_reg_w_init.v verilogSource work hdl/convert_type.v verilogSource work hdl/xlclockdriver_rd.v verilogSource work hdl/ip_pid_controller_entity_declarations.v verilogSource work hdl/ip_pid_controller.v verilogSource work xilinx_verilogbehavioralsimulation_view_fileset ip_pid_controller_c_addsub_v12_0_0/ip_pid_controller_c_addsub_v12_0_0.xci xci ip_pid_controller_c_addsub_v12_0_1/ip_pid_controller_c_addsub_v12_0_1.xci xci ip_pid_controller_mult_gen_v12_0_0/ip_pid_controller_mult_gen_v12_0_0.xci xci ip_pid_controller_div_gen_v5_1_0/ip_pid_controller_div_gen_v5_1_0.xci xci ip_pid_controller_c_counter_binary_v12_0_0/ip_pid_controller_c_counter_binary_v12_0_0.xci xci hdl/conv_pkg.v verilogSource true work hdl/synth_reg.v verilogSource work hdl/synth_reg_w_init.v verilogSource work hdl/convert_type.v verilogSource work hdl/xlclockdriver_rd.v verilogSource work hdl/ip_pid_controller_entity_declarations.v verilogSource work hdl/ip_pid_controller.v verilogSource work xilinx_xpgui_view_fileset xgui/ip_pid_controller_v1_0.tcl tclSource XGUI_VERSION_2 xilinx_utilityxitfiles_view_fileset sysgen_icon_100.png image LOGO This IP was generated from System Generator. All changes must be made in SysGen model. Component_Name ip_pid_controller_v1_0 zynq /motor_control ip_pid_controller 29608450 false 2014-04-28T13:34:48Z 2013.4