// ------------------------------------------------------------- // // File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\PWM.v // Created: 2014-09-08 14:12:09 // // Generated by MATLAB 8.2 and HDL Coder 3.3 // // ------------------------------------------------------------- // ------------------------------------------------------------- // // Module: PWM // Source Path: controllerPeripheralHdlAdi/PWM // Hierarchy Level: 1 // // ------------------------------------------------------------- `timescale 1 ns / 1 ns module PWM ( CLK_IN, reset, enb, c_0, c_1, c_2, pwm_0, pwm_1, pwm_2 ); input CLK_IN; input reset; input enb; input [15:0] c_0; // uint16 input [15:0] c_1; // uint16 input [15:0] c_2; // uint16 output pwm_0; // boolean output pwm_1; // boolean output pwm_2; // boolean wire [15:0] Timer_Period_Clock_Cycles_out1; // uint16 wire [15:0] Chart_out1; // uint16 wire [15:0] c [0:2]; // uint16 [3] wire [15:0] Add_out1 [0:2]; // uint16 [3] wire [15:0] Add_out1_0; // uint16 wire Relational_Operator_relop1; wire [15:0] Add_out1_1; // uint16 wire Relational_Operator_relop2; wire [15:0] Add_out1_2; // uint16 wire Relational_Operator_relop3; wire [0:2] Relational_Operator_out1; // boolean [3] wire Relational_Operator_out1_0; wire [0:2] Compare_To_Zero_out1; // boolean [3] wire Compare_To_Zero_out1_0; wire Relational_Operator_out1_0_1; wire Relational_Operator_out1_1; wire Compare_To_Zero_out1_1; wire Relational_Operator_out1_1_1; wire Relational_Operator_out1_2; wire Compare_To_Zero_out1_2; wire Relational_Operator_out1_2_1; // /Timer Period Clock Cycles assign Timer_Period_Clock_Cycles_out1 = 16'd1000; // /Chart Chart u_Chart (.CLK_IN(CLK_IN), .reset(reset), .enb(enb), .CounterMax(Timer_Period_Clock_Cycles_out1), // uint16 .count(Chart_out1) // uint16 ); assign c[0] = c_0; assign c[1] = c_1; assign c[2] = c_2; // /Add assign Add_out1[0] = Timer_Period_Clock_Cycles_out1 - c[0]; assign Add_out1[1] = Timer_Period_Clock_Cycles_out1 - c[1]; assign Add_out1[2] = Timer_Period_Clock_Cycles_out1 - c[2]; assign Add_out1_0 = Add_out1[0]; assign Relational_Operator_relop1 = (Chart_out1 >= Add_out1_0 ? 1'b1 : 1'b0); assign Add_out1_1 = Add_out1[1]; assign Relational_Operator_relop2 = (Chart_out1 >= Add_out1_1 ? 1'b1 : 1'b0); assign Add_out1_2 = Add_out1[2]; // /Relational Operator assign Relational_Operator_relop3 = (Chart_out1 >= Add_out1_2 ? 1'b1 : 1'b0); assign Relational_Operator_out1[0] = Relational_Operator_relop1; assign Relational_Operator_out1[1] = Relational_Operator_relop2; assign Relational_Operator_out1[2] = Relational_Operator_relop3; assign Relational_Operator_out1_0 = Relational_Operator_out1[0]; // /Compare To Zero assign Compare_To_Zero_out1[0] = (c[0] != 16'b0000000000000000 ? 1'b1 : 1'b0); assign Compare_To_Zero_out1[1] = (c[1] != 16'b0000000000000000 ? 1'b1 : 1'b0); assign Compare_To_Zero_out1[2] = (c[2] != 16'b0000000000000000 ? 1'b1 : 1'b0); assign Compare_To_Zero_out1_0 = Compare_To_Zero_out1[0]; assign Relational_Operator_out1_0_1 = Relational_Operator_out1_0 & Compare_To_Zero_out1_0; assign pwm_0 = Relational_Operator_out1_0_1; assign Relational_Operator_out1_1 = Relational_Operator_out1[1]; assign Compare_To_Zero_out1_1 = Compare_To_Zero_out1[1]; assign Relational_Operator_out1_1_1 = Relational_Operator_out1_1 & Compare_To_Zero_out1_1; assign pwm_1 = Relational_Operator_out1_1_1; assign Relational_Operator_out1_2 = Relational_Operator_out1[2]; assign Compare_To_Zero_out1_2 = Compare_To_Zero_out1[2]; // /Logical Operator assign Relational_Operator_out1_2_1 = Relational_Operator_out1_2 & Compare_To_Zero_out1_2; assign pwm_2 = Relational_Operator_out1_2_1; endmodule // PWM