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`timescale 1ns/100ps

//------------------------------------------------------------------------------   
//----------- Module Declaration -----------------------------------------------
//------------------------------------------------------------------------------ 
module clk_div
    (
        // Clock and Reset signals
        input 			clk_i,
        input 			reset_n_i,
		
		// Clock divider
		input 			new_div_i,
		input   [31:0] 	div_i,
		input			new_phase_inc_i,
		input   [31:0] 	phase_inc_i,
        
		// Divided clock output
		output	reg		reg_update_rdy_o,
		output 			clk_o,
		output 	[31:0]	phase_o
    );

//------------------------------------------------------------------------------
//----------- Registers Declarations -------------------------------------------
//------------------------------------------------------------------------------
reg [31:0] div;
reg [31:0] div_cnt;
reg [31:0] phase;
reg [31:0] phase_inc;
reg        clk_div;

//------------------------------------------------------------------------------
//----------- Assign/Always Blocks ---------------------------------------------
//------------------------------------------------------------------------------
assign clk_o 	= clk_div;
assign phase_o 	= phase;

// Register update logic
always @(posedge clk_i)
begin
    if(reset_n_i == 1'b0)
    begin
        div   		<= 'd0;
		phase_inc	<= 'd0;
		reg_update_rdy_o <= 1'b0;
    end
    else
    begin
		if(new_div_i == 1'b1)
		begin
			div <= div_i;			
		end
		if(new_phase_inc_i == 1'b1)
		begin
			phase_inc <= phase_inc_i;			
		end
		reg_update_rdy_o <= new_div_i | new_phase_inc_i;		
    end
end

// Clock division logic
always @(posedge clk_i)
begin
    if(reset_n_i == 1'b0)
    begin
		clk_div	<= 'd1;
		phase   <= 'd0;
    end
    else
    begin
        if(div_cnt < div)
		begin
			div_cnt <= div_cnt + 'd1;
		end
		else
		begin
			div_cnt <= 'd1;
			//clk_div <= ~clk_div;
		end
		phase <= phase + phase_inc;
		clk_div <= phase[31];
    end
end

endmodule