// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module util_wfifo (

  rstn,
  clk,

  src_wr,
  src_wdata,
  src_wovf,
  dst_wr,
  dst_wdata,
  dst_wovf,

  fifo_rst,
  fifo_wr,
  fifo_wdata,
  fifo_wfull,
  fifo_wovf,
  fifo_rd,
  fifo_rdata,
  fifo_rempty);

  // parameters (read (S) bus width must be greater than write (M))

  parameter SRC_DATA_WIDTH = 32;
  parameter DST_DATA_WIDTH = 64;
 
  // common clock

  input                           rstn;
  input                           clk;

  // master/slave write 

  input                           src_wr;
  input   [SRC_DATA_WIDTH-1:0]    src_wdata;
  output                          src_wovf;
  output                          dst_wr;
  output  [DST_DATA_WIDTH-1:0]    dst_wdata;
  input                           dst_wovf;

  // fifo interface

  output                          fifo_rst;
  output                          fifo_wr;
  output  [SRC_DATA_WIDTH-1:0]    fifo_wdata;
  input                           fifo_wfull;
  input                           fifo_wovf;
  output                          fifo_rd;
  input   [DST_DATA_WIDTH-1:0]    fifo_rdata;
  input                           fifo_rempty;

  // internal registers

  reg                             fifo_rst = 'd0;
  reg                             src_wovf = 'd0;
  reg                             dst_wr = 'd0;

  // defaults

  always @(posedge clk or negedge rstn) begin
    if (rstn == 1'b0) begin
      fifo_rst <= 1'b1;
    end else begin
      fifo_rst <= 1'b0;
    end
  end

  // write is pass through (fifo can never become full nor overflow)

  assign fifo_wr = src_wr;

  genvar m;
  generate
  for (m = 0; m < SRC_DATA_WIDTH; m = m + 1) begin: g_wdata
  assign fifo_wdata[m] = src_wdata[(SRC_DATA_WIDTH-1)-m];
  end
  endgenerate

  always @(posedge clk) begin
    src_wovf <= dst_wovf | fifo_wfull | fifo_wovf;
  end

  // read is non-destructive

  assign fifo_rd = ~fifo_rempty;

  always @(posedge clk) begin
    dst_wr <= fifo_rd;
  end
  
  genvar s;
  generate
  for (s = 0; s < DST_DATA_WIDTH; s = s + 1) begin: g_rdata
  assign dst_wdata[s] = fifo_rdata[(DST_DATA_WIDTH-1)-s];
  end
  endgenerate

endmodule

// ***************************************************************************
// ***************************************************************************