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// ***************************************************************************
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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps

module ad_tdd_sync (

  // clock & reset

  clk,
  rst,

  // control signals

  tdd_sync_en,          // synchronization enabled
  tdd_term_type,        // master or slave
  tdd_enable_in,        // tdd_enable signal asserted by software
  tdd_enable_out,       // synchronized tdd_enable

  // sync interface

  sync_req,             // sync request generated by master
  sync_ack,              // sync acknowledge generated by slave

  // debug
  sync_dbg

);

  input         clk;
  input         rst;

  input         tdd_sync_en;
  input         tdd_term_type;
  input         tdd_enable_in;
  output        tdd_enable_out;

  inout         sync_req;
  inout         sync_ack;

  output  [5:0] sync_dbg;

  reg           tdd_enable_out = 1'b0;
  reg           tdd_enable_synced = 1'b0;
  reg           tdd_enable_d = 1'b0;
  reg           sync_req_i = 1'b0;
  reg           sync_ack_i = 1'b0;

  reg     [2:0] pulse_width = 3'h7;

  wire          sync_ack_o_s;
  wire          sync_req_o_s;
  wire          sync_req_t_s;
  wire          sync_ack_t_s;

  // the sync module can be bypassed

  always @(posedge clk) begin
    if (rst == 1) begin
      tdd_enable_out <= 1'b0;
    end else begin
      tdd_enable_out <= (tdd_sync_en) ? tdd_enable_synced : tdd_enable_in;
    end
  end

  // iobuffers for the syncronization lines

  assign sync_req_t_s = ~tdd_term_type;
  assign sync_ack_t_s = tdd_term_type;

  assign sync_dbg = {sync_ack_i_s,
                     sync_ack_o_s,
                     sync_ack_t_s,
                     sync_req_i,
                     sync_req_o_s,
                     sync_req_t_s};

  ad_iobuf #(
    .DATA_WIDTH(1)
  ) i_sync_req_iobuf (
    .dio_t (sync_req_t_s),
    .dio_i (sync_req_i),
    .dio_o (sync_req_o_s),
    .dio_p (sync_req)
  );

  ad_iobuf #(
    .DATA_WIDTH(1)
  ) i_sync_ack_iobuf (
    .dio_t (sync_ack_i_s),
    .dio_i (sync_ack_i),
    .dio_o (sync_ack_o_s),
    .dio_p (sync_ack)
  );

  always @(posedge clk) begin
    if (rst == 1) begin
      tdd_enable_d <= 1'b0;
      sync_req_i <= 1'b0;
      sync_ack_i <= 1'b0;
      pulse_width <= 3'h7;
    end else begin

      tdd_enable_d <= tdd_enable_in;
      // device is master
      if (tdd_term_type == 1) begin

        if (~tdd_enable_d & tdd_enable_in == 1'b1) begin // generate sync request
          sync_req_i <= 1'b1;
          pulse_width <= 1'b0;
        end else begin
          pulse_width <= (pulse_width < 3'h7) ? pulse_width + 1 : pulse_width;
          sync_req_i <= (pulse_width == 3'h7) ? 1'b0 : 1'b1;
        end

        if (sync_ack_o_s == 1'b1) begin // sync acknowledge arrived
          tdd_enable_synced <= tdd_enable_in;
        end else begin
          tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced;
        end
      // device is slave
      end else begin
        if (sync_req_o_s == 1'b1) begin
          tdd_enable_synced <= tdd_enable_in;
          sync_ack_i <= 1'b1;
        end else begin
          tdd_enable_synced <= (tdd_enable_in == 1'b0) ? 1'b0 : tdd_enable_synced;
          sync_ack_i <= 1'b0;
        end
      end
    end
  end

endmodule