####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := jesd204_tx

GENERIC_DEPS += jesd204_tx.v
GENERIC_DEPS += jesd204_tx_ctrl.v
GENERIC_DEPS += jesd204_tx_lane.v

XILINX_DEPS += jesd204_tx_constr.ttcl
XILINX_DEPS += jesd204_tx_header.v
XILINX_DEPS += jesd204_tx_ip.tcl
XILINX_DEPS += jesd204_tx_lane_64b.v

XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_cfg_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ctrl_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_event_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_ilas_config_rtl.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status.xml
XILINX_DEPS += ../../jesd204/interfaces/jesd204_tx_status_rtl.xml
XILINX_DEPS += bd/bd.tcl

XILINX_LIB_DEPS += jesd204/jesd204_common
XILINX_LIB_DEPS += util_cdc

XILINX_INTERFACE_DEPS += jesd204/interfaces

INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../jesd204_common/jesd204_eof_generator.v
INTEL_DEPS += ../jesd204_common/jesd204_lmfc.v
INTEL_DEPS += ../jesd204_common/jesd204_scrambler.v
INTEL_DEPS += ../jesd204_common/pipeline_stage.v
INTEL_DEPS += jesd204_tx_constr.sdc
INTEL_DEPS += jesd204_tx_hw.tcl

include ../../scripts/library.mk