// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
// 
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/1ps

module axi_adxcvr_mdrp (

  input           up_rstn,
  input           up_clk,

  input   [ 7:0]  up_sel,
  input           up_enb,
  input   [15:0]  up_rdata_in,
  input           up_ready_in,
  input   [15:0]  up_rdata,
  input           up_ready,
  output  [15:0]  up_rdata_out,
  output          up_ready_out);

  // parameters

  parameter   integer XCVR_ID = 0;

  // internal registers

  reg             up_ready_d = 'd0;
  reg     [15:0]  up_rdata_int = 'd0;
  reg             up_ready_int = 'd0;
  reg     [15:0]  up_rdata_m_in = 'd0;
  reg             up_ready_m_in = 'd0;
  reg     [15:0]  up_rdata_m = 'd0;
  reg             up_ready_m = 'd0;

  // internal signals

  wire            up_ready_s;
  wire    [15:0]  up_rdata_m_s;
  wire            up_ready_m_s;

  // disable if not selected

  assign up_rdata_out = up_rdata_int;
  assign up_ready_out = up_ready_int;

  assign up_ready_s = up_ready_m & up_ready_m_in;
  assign up_rdata_m_s = up_rdata_m | up_rdata_m_in;
  assign up_ready_m_s = up_ready_s & ~up_ready_d;

  always @(negedge up_rstn or posedge up_clk) begin
    if (up_rstn == 1'b0) begin
      up_ready_d <= 1'd0;
      up_rdata_int <= 16'd0;
      up_ready_int <= 1'b0;
    end else begin
      up_ready_d <= up_ready_s;
      case (up_sel)
        8'hff: begin
          up_rdata_int <= up_rdata_m_s;
          up_ready_int <= up_ready_m_s;
        end
        XCVR_ID: begin
          up_rdata_int <= up_rdata;
          up_ready_int <= up_ready;
        end
        default: begin
          up_rdata_int <= up_rdata_in;
          up_ready_int <= up_ready_int;
        end
      endcase
    end
  end

  always @(negedge up_rstn or posedge up_clk) begin
    if (up_rstn == 1'b0) begin
      up_rdata_m_in <= 16'd0;
      up_ready_m_in <= 1'b0;
      up_rdata_m <= 16'd0;
      up_ready_m <= 1'b0;
    end else begin
      if (up_ready_in == 1'b1) begin
        up_rdata_m_in <= up_rdata_in;
        up_ready_m_in <= 1'b1;
      end else if (up_enb == 1'b1) begin
        up_rdata_m_in <= 16'd0;
        up_ready_m_in <= 1'b0;
      end
      if (up_ready == 1'b1) begin
        up_rdata_m <= up_rdata;
        up_ready_m <= 1'b1;
      end else if (up_enb == 1'b1) begin
        up_rdata_m <= 16'd0;
        up_ready_m <= 1'b0;
      end
    end
  end

endmodule     

// ***************************************************************************
// ***************************************************************************