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`timescale 1ns / 1ps

module axi_ad9162_channel (

    // dac interface
    
    dac_clk,
    dac_rst,
    dac_enable,
    dac_data,
    dma_data,
    
    // processor interface
    
    dac_data_sync,
    dac_dds_format,
    
    // bus interface
    
    up_rstn,
    up_clk,
    up_wreq,
    up_waddr,
    up_wdata,
    up_wack,
    up_rreq,
    up_raddr,
    up_rdata,
    up_rack);
    
    // parameters
    
    parameter CHANNEL_ID = 32'h0;
    parameter DATAPATH_DISABLE = 0;
    
    // dac interface
    
    input             dac_clk;
    input             dac_rst;
    output            dac_enable;
    output  [255:0]   dac_data;
    input   [255:0]   dma_data;
    
    // processor interface
    
    input             dac_data_sync;
    input             dac_dds_format;
    
    // bus interface
    
    input             up_rstn;
    input             up_clk;
    input             up_wreq;
    input   [ 13:0]   up_waddr;
    input   [ 31:0]   up_wdata;
    output            up_wack;
    input             up_rreq;
    input   [ 13:0]   up_raddr;
    output  [ 31:0]   up_rdata;
    output            up_rack;
    
    // internal registers
    
    reg               dac_enable = 'd0;
    reg     [255:0]   dac_data = 'd0;
    reg     [255:0]   dac_pn7_data = 'd0;
    reg     [255:0]   dac_pn15_data = 'd0;
    reg     [ 15:0]   dac_dds_phase_00_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_00_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_01_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_01_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_02_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_02_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_03_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_03_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_04_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_04_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_05_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_05_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_06_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_06_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_07_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_07_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_08_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_08_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_09_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_09_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_10_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_10_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_11_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_11_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_12_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_12_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_13_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_13_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_14_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_14_1 = 'd0;
    reg     [ 15:0]   dac_dds_phase_15_0 = 'd0;
    reg     [ 15:0]   dac_dds_phase_15_1 = 'd0;
    reg     [ 15:0]   dac_dds_incr_0 = 'd0;
    reg     [ 15:0]   dac_dds_incr_1 = 'd0;
    reg     [255:0]   dac_dds_data = 'd0;
    
    // internal signals
    
    wire    [ 15:0]   dac_dds_scale_1_s;
    wire    [ 15:0]   dac_dds_init_1_s;
    wire    [ 15:0]   dac_dds_incr_1_s;
    wire    [ 15:0]   dac_dds_scale_2_s;
    wire    [ 15:0]   dac_dds_init_2_s;
    wire    [ 15:0]   dac_dds_incr_2_s;
    wire    [ 15:0]   dac_pat_data_1_s;
    wire    [ 15:0]   dac_pat_data_2_s;
    wire    [  3:0]   dac_data_sel_s;
    wire              dac_iq_mode_s;
    wire    [255:0]   dac_pn7_data_i_s;
    wire    [255:0]   dac_pn15_data_i_s;
    wire    [255:0]   dac_pn7_data_s;
    wire    [255:0]   dac_pn15_data_s;
    wire    [255:0]   dac_pat_data_s;
    wire    [255:0]   dac_dds_data_s;
    
    genvar n;

    // PN7 function
    
    function [255:0] pn7;
         input [7:0] din;
         reg   [255:0] dout;
         reg   [15:0] dout16;
         reg   [7:0] din_reg;
         integer i;
         integer j;
         begin
         din_reg = din;
           for ( j=0 ; j<16 ; j=j+1)begin
             for ( i=0 ; i<16 ; i= i+1)begin
                 din_reg = {din_reg,din_reg[6]^din_reg[5]};
                 dout16[15-i] = din_reg[0];
              end
              dout = {dout16,dout[255:16]};
           end         
           pn7 = dout;
         end
    endfunction
    
    // PN15 function
    
    function [255:0] pn15;
         input [15:0] din;
         reg   [255:0] dout;
         reg   [15:0] dout16;
         reg   [15:0] din_reg;
         integer i;
         integer j;
         begin
         din_reg = din;
           for (j=0 ; j<16 ; j=j+1)begin
             for (i=0 ; i<16 ; i= i+1)begin
                 din_reg = {din_reg,din_reg[14]^din_reg[13]};
                 dout16[15-i] = din_reg[0];
              end
              dout = {dout16,dout[255:16]};
           end         
           pn15 = dout;
         end
    endfunction
    
    assign dac_pn7_data_i_s = ~dac_pn7_data;
    assign dac_pn15_data_i_s = ~dac_pn15_data;
    
    assign dac_pn7_data_s = dac_pn7_data;
    assign dac_pn15_data_s = dac_pn15_data;

    generate
    for (n = 0; n < 8; n = n + 1) begin: g_dac_pat_data
    assign dac_pat_data_s[((32*n)+31):((32*n)+16)] = dac_pat_data_2_s;
    assign dac_pat_data_s[((32*n)+15):((32*n)+ 0)] = dac_pat_data_1_s;
    end
    endgenerate
    
    // dac data select
    
    always @(posedge dac_clk) begin
      dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0;
      case (dac_data_sel_s)
        4'h7: dac_data <= dac_pn15_data_s;
        4'h6: dac_data <= dac_pn7_data_s;
        4'h5: dac_data <= dac_pn15_data_i_s;
        4'h4: dac_data <= dac_pn7_data_i_s;
        4'h3: dac_data <= 256'd0;
        4'h2: dac_data <= dma_data;
        4'h1: dac_data <= dac_pat_data_s;
        default: dac_data <= dac_dds_data;
      endcase
    end
    
    // pn registers
    
    always @(posedge dac_clk) begin
      if (dac_data_sync == 1'b1) begin
        dac_pn7_data <= {255{1'd1}};
        dac_pn15_data <= {255{1'd1}};
      end else begin
        dac_pn7_data <= pn7(dac_pn7_data[247:240]);
        dac_pn15_data <= pn15(dac_pn15_data[255:240]);
      end
    end
    
    // dds
    
    always @(posedge dac_clk) begin
      if (dac_data_sync == 1'b0) begin
        dac_dds_phase_00_0 <= dac_dds_phase_00_0 + dac_dds_incr_0;
        dac_dds_phase_00_1 <= dac_dds_phase_00_1 + dac_dds_incr_1;
        dac_dds_phase_01_0 <= dac_dds_phase_01_0 + dac_dds_incr_0;
        dac_dds_phase_01_1 <= dac_dds_phase_01_1 + dac_dds_incr_1;
        dac_dds_phase_02_0 <= dac_dds_phase_02_0 + dac_dds_incr_0;
        dac_dds_phase_02_1 <= dac_dds_phase_02_1 + dac_dds_incr_1;
        dac_dds_phase_03_0 <= dac_dds_phase_03_0 + dac_dds_incr_0;
        dac_dds_phase_03_1 <= dac_dds_phase_03_1 + dac_dds_incr_1;
        dac_dds_phase_04_0 <= dac_dds_phase_04_0 + dac_dds_incr_0;
        dac_dds_phase_04_1 <= dac_dds_phase_04_1 + dac_dds_incr_1;
        dac_dds_phase_05_0 <= dac_dds_phase_05_0 + dac_dds_incr_0;
        dac_dds_phase_05_1 <= dac_dds_phase_05_1 + dac_dds_incr_1;
        dac_dds_phase_06_0 <= dac_dds_phase_06_0 + dac_dds_incr_0;
        dac_dds_phase_06_1 <= dac_dds_phase_06_1 + dac_dds_incr_1;
        dac_dds_phase_07_0 <= dac_dds_phase_07_0 + dac_dds_incr_0;
        dac_dds_phase_07_1 <= dac_dds_phase_07_1 + dac_dds_incr_1;
        dac_dds_phase_08_0 <= dac_dds_phase_08_0 + dac_dds_incr_0;
        dac_dds_phase_08_1 <= dac_dds_phase_08_1 + dac_dds_incr_1;
        dac_dds_phase_09_0 <= dac_dds_phase_09_0 + dac_dds_incr_0;
        dac_dds_phase_09_1 <= dac_dds_phase_09_1 + dac_dds_incr_1;
        dac_dds_phase_10_0 <= dac_dds_phase_10_0 + dac_dds_incr_0;
        dac_dds_phase_10_1 <= dac_dds_phase_10_1 + dac_dds_incr_1;
        dac_dds_phase_11_0 <= dac_dds_phase_11_0 + dac_dds_incr_0;
        dac_dds_phase_11_1 <= dac_dds_phase_11_1 + dac_dds_incr_1;
        dac_dds_phase_12_0 <= dac_dds_phase_12_0 + dac_dds_incr_0;
        dac_dds_phase_12_1 <= dac_dds_phase_12_1 + dac_dds_incr_1;
        dac_dds_phase_13_0 <= dac_dds_phase_13_0 + dac_dds_incr_0;
        dac_dds_phase_13_1 <= dac_dds_phase_13_1 + dac_dds_incr_1;
        dac_dds_phase_14_0 <= dac_dds_phase_14_0 + dac_dds_incr_0;
        dac_dds_phase_14_1 <= dac_dds_phase_14_1 + dac_dds_incr_1;
        dac_dds_phase_15_0 <= dac_dds_phase_15_0 + dac_dds_incr_0;
        dac_dds_phase_15_1 <= dac_dds_phase_15_1 + dac_dds_incr_1;
        dac_dds_incr_0 <= dac_dds_incr_0;
        dac_dds_incr_1 <= dac_dds_incr_1;
        dac_dds_data <= dac_dds_data_s;
      end else if (dac_iq_mode_s == 1'b1) begin
        dac_dds_phase_00_0 <= dac_dds_init_1_s;
        dac_dds_phase_00_1 <= dac_dds_init_2_s;
        dac_dds_phase_01_0 <= dac_dds_phase_00_0 + 16'h4000;
        dac_dds_phase_01_1 <= dac_dds_phase_00_1 + 16'h4000;
        dac_dds_phase_02_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
        dac_dds_phase_02_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
        dac_dds_phase_03_0 <= dac_dds_phase_02_0 + 16'h4000;
        dac_dds_phase_03_1 <= dac_dds_phase_02_1 + 16'h4000;
        dac_dds_phase_04_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
        dac_dds_phase_04_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
        dac_dds_phase_05_0 <= dac_dds_phase_04_0 + 16'h4000;
        dac_dds_phase_05_1 <= dac_dds_phase_04_1 + 16'h4000;
        dac_dds_phase_06_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
        dac_dds_phase_06_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
        dac_dds_phase_07_0 <= dac_dds_phase_06_0 + 16'h4000;
        dac_dds_phase_07_1 <= dac_dds_phase_06_1 + 16'h4000;
        dac_dds_phase_08_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
        dac_dds_phase_08_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
        dac_dds_phase_09_0 <= dac_dds_phase_08_0 + 16'h4000;
        dac_dds_phase_09_1 <= dac_dds_phase_08_1 + 16'h4000;
        dac_dds_phase_10_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
        dac_dds_phase_10_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
        dac_dds_phase_11_0 <= dac_dds_phase_10_0 + 16'h4000;
        dac_dds_phase_11_1 <= dac_dds_phase_10_1 + 16'h4000;
        dac_dds_phase_12_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
        dac_dds_phase_12_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
        dac_dds_phase_13_0 <= dac_dds_phase_12_0 + 16'h4000;
        dac_dds_phase_13_1 <= dac_dds_phase_12_1 + 16'h4000;
        dac_dds_phase_14_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
        dac_dds_phase_14_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
        dac_dds_phase_15_0 <= dac_dds_phase_14_0 + 16'h4000;
        dac_dds_phase_15_1 <= dac_dds_phase_14_1 + 16'h4000;
        dac_dds_incr_0 <= {dac_dds_incr_1_s[12:0], 3'd0};
        dac_dds_incr_1 <= {dac_dds_incr_2_s[12:0], 3'd0};
        dac_dds_data <= 256'd0;
      end else begin
        dac_dds_phase_00_0 <= dac_dds_init_1_s;
        dac_dds_phase_00_1 <= dac_dds_init_2_s;
        dac_dds_phase_01_0 <= dac_dds_phase_00_0 + dac_dds_incr_1_s;
        dac_dds_phase_01_1 <= dac_dds_phase_00_1 + dac_dds_incr_2_s;
        dac_dds_phase_02_0 <= dac_dds_phase_01_0 + dac_dds_incr_1_s;
        dac_dds_phase_02_1 <= dac_dds_phase_01_1 + dac_dds_incr_2_s;
        dac_dds_phase_03_0 <= dac_dds_phase_02_0 + dac_dds_incr_1_s;
        dac_dds_phase_03_1 <= dac_dds_phase_02_1 + dac_dds_incr_2_s;
        dac_dds_phase_04_0 <= dac_dds_phase_03_0 + dac_dds_incr_1_s;
        dac_dds_phase_04_1 <= dac_dds_phase_03_1 + dac_dds_incr_2_s;
        dac_dds_phase_05_0 <= dac_dds_phase_04_0 + dac_dds_incr_1_s;
        dac_dds_phase_05_1 <= dac_dds_phase_04_1 + dac_dds_incr_2_s;
        dac_dds_phase_06_0 <= dac_dds_phase_05_0 + dac_dds_incr_1_s;
        dac_dds_phase_06_1 <= dac_dds_phase_05_1 + dac_dds_incr_2_s;
        dac_dds_phase_07_0 <= dac_dds_phase_06_0 + dac_dds_incr_1_s;
        dac_dds_phase_07_1 <= dac_dds_phase_06_1 + dac_dds_incr_2_s;
        dac_dds_phase_08_0 <= dac_dds_phase_07_0 + dac_dds_incr_1_s;
        dac_dds_phase_08_1 <= dac_dds_phase_07_1 + dac_dds_incr_2_s;
        dac_dds_phase_09_0 <= dac_dds_phase_08_0 + dac_dds_incr_1_s;
        dac_dds_phase_09_1 <= dac_dds_phase_08_1 + dac_dds_incr_2_s;
        dac_dds_phase_10_0 <= dac_dds_phase_09_0 + dac_dds_incr_1_s;
        dac_dds_phase_10_1 <= dac_dds_phase_09_1 + dac_dds_incr_2_s;
        dac_dds_phase_11_0 <= dac_dds_phase_10_0 + dac_dds_incr_1_s;
        dac_dds_phase_11_1 <= dac_dds_phase_10_1 + dac_dds_incr_2_s;
        dac_dds_phase_12_0 <= dac_dds_phase_11_0 + dac_dds_incr_1_s;
        dac_dds_phase_12_1 <= dac_dds_phase_11_1 + dac_dds_incr_2_s;
        dac_dds_phase_13_0 <= dac_dds_phase_12_0 + dac_dds_incr_1_s;
        dac_dds_phase_13_1 <= dac_dds_phase_12_1 + dac_dds_incr_2_s;
        dac_dds_phase_14_0 <= dac_dds_phase_13_0 + dac_dds_incr_1_s;
        dac_dds_phase_14_1 <= dac_dds_phase_13_1 + dac_dds_incr_2_s;
        dac_dds_phase_15_0 <= dac_dds_phase_14_0 + dac_dds_incr_1_s;
        dac_dds_phase_15_1 <= dac_dds_phase_14_1 + dac_dds_incr_2_s;
        dac_dds_incr_0 <= {dac_dds_incr_1_s[11:0], 4'd0};
        dac_dds_incr_1 <= {dac_dds_incr_2_s[11:0], 4'd0};
        dac_dds_data <= 256'd0;
      end
    end
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[15:0] = 16'd0;
    end else begin
    ad_dds i_dds_00 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_00_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_00_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[15:0]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[31:16] = 16'd0;
    end else begin
    ad_dds i_dds_01 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_01_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_01_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[31:16]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[47:32] = 16'd0;
    end else begin
    ad_dds i_dds_02 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_02_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_02_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[47:32]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[63:48] = 16'd0;
    end else begin
    ad_dds i_dds_03 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_03_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_03_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[63:48]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[79:64] = 16'd0;
    end else begin
    ad_dds i_dds_04 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_04_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_04_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[79:64]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[95:80] = 16'd0;
    end else begin
    ad_dds i_dds_05 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_05_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_05_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[95:80]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[111:96] = 16'd0;
    end else begin
    ad_dds i_dds_06 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_06_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_06_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[111:96]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[127:112] = 16'd0;
    end else begin
    ad_dds i_dds_07 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_07_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_07_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[127:112]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[143:128] = 16'd0;
    end else begin
    ad_dds i_dds_08 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_08_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_08_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[143:128]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[159:144] = 16'd0;
    end else begin
    ad_dds i_dds_09 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_09_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_09_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[159:144]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[175:160] = 16'd0;
    end else begin
    ad_dds i_dds_10 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_10_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_10_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[175:160]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[191:176] = 16'd0;
    end else begin
    ad_dds i_dds_11 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_11_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_11_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[191:176]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[207:192] = 16'd0;
    end else begin
    ad_dds i_dds_12 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_12_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_12_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[207:192]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[223:208] = 16'd0;
    end else begin
    ad_dds i_dds_13 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_13_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_13_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[223:208]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[239:224] = 16'd0;
    end else begin
    ad_dds i_dds_14 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_14_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_14_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[239:224]));
    end
    endgenerate
    
    generate
    if (DATAPATH_DISABLE == 1) begin
    assign dac_dds_data_s[255:240] = 16'd0;
    end else begin
    ad_dds i_dds_15 (
      .clk (dac_clk),
      .dds_format (dac_dds_format),
      .dds_phase_0 (dac_dds_phase_15_0),
      .dds_scale_0 (dac_dds_scale_1_s),
      .dds_phase_1 (dac_dds_phase_15_1),
      .dds_scale_1 (dac_dds_scale_2_s),
      .dds_data (dac_dds_data_s[255:240]));
    end
    endgenerate
    
    // single channel processor
    
    up_dac_channel #(.CHANNEL_ID(CHANNEL_ID)) i_up_dac_channel (
      .dac_clk (dac_clk),
      .dac_rst (dac_rst),
      .dac_dds_scale_1 (dac_dds_scale_1_s),
      .dac_dds_init_1 (dac_dds_init_1_s),
      .dac_dds_incr_1 (dac_dds_incr_1_s),
      .dac_dds_scale_2 (dac_dds_scale_2_s),
      .dac_dds_init_2 (dac_dds_init_2_s),
      .dac_dds_incr_2 (dac_dds_incr_2_s),
      .dac_pat_data_1 (dac_pat_data_1_s),
      .dac_pat_data_2 (dac_pat_data_2_s),
      .dac_data_sel (dac_data_sel_s),
      .dac_iq_mode (dac_iq_mode_s),
      .dac_iq_mode (),
      .dac_iqcor_enb (),
      .dac_iqcor_coeff_1 (),
      .dac_iqcor_coeff_2 (),
      .up_usr_datatype_be (),
      .up_usr_datatype_signed (),
      .up_usr_datatype_shift (),
      .up_usr_datatype_total_bits (),
      .up_usr_datatype_bits (),
      .up_usr_interpolation_m (),
      .up_usr_interpolation_n (),
      .dac_usr_datatype_be (1'b0),
      .dac_usr_datatype_signed (1'b1),
      .dac_usr_datatype_shift (8'd0),
      .dac_usr_datatype_total_bits (8'd16),
      .dac_usr_datatype_bits (8'd16),
      .dac_usr_interpolation_m (16'd1),
      .dac_usr_interpolation_n (16'd1),
      .up_rstn (up_rstn),
      .up_clk (up_clk),
      .up_wreq (up_wreq),
      .up_waddr (up_waddr),
      .up_wdata (up_wdata),
      .up_wack (up_wack),
      .up_rreq (up_rreq),
      .up_raddr (up_raddr),
      .up_rdata (up_rdata),
      .up_rack (up_rack));

endmodule

// ***************************************************************************
// ***************************************************************************