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// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/1ps

module ad_tdd_sync (

  // clock & reset

  clk,
  rst,

  // control signals

  sync_en,              // synchronization enabled
  device_type,          // master or slave
  sync_period,          // periodicity of the sync pulse,

  enable_in,            // tdd enable signal asserted by software
  enable_out,           // synchronized tdd_enable

  // sync interface

  sync_out,             // sync output for slave
  sync_in,              // sync input

  resync                // resync pulse for slave device

);

  input           clk;
  input           rst;

  input           sync_en;
  input           device_type;
  input   [31:0]  sync_period;

  input           enable_in;
  output          enable_out;

  output          sync_out;
  input           sync_in;

  output          resync;

  // internal registers

  reg             enable_out = 1'b0;
  reg             enable_synced = 1'b0;
  reg             sync_in_d = 1'b0;

  reg             sync_out = 1'b0;
  reg             resync = 1'b0;

  reg     [ 2:0]  pulse_width = 3'h7;

  reg     [31:0]  pulse_counter = 32'h0;

  // the sync module can be bypassed

  always @(posedge clk) begin
    if (rst == 1) begin
      enable_out <= 1'b0;
    end else begin
      enable_out <= (sync_en) ? enable_synced : enable_in;
    end
  end

  // generate sync pulse

  always @(posedge clk) begin
    if(rst == 1) begin
      pulse_counter <= 0;
      pulse_width <= 3'h7;
      sync_out <= 1'h0;
    end else begin
      if (device_type == 1) begin
        pulse_counter <= (pulse_counter < sync_period) ? pulse_counter + 1 : 32'h0;
        if(pulse_counter == sync_period) begin
          sync_out <= enable_in;
          pulse_width <= 3'h0;
        end else begin
          pulse_width <= (pulse_width < 3'h7) ? pulse_width + 1 : pulse_width;
          sync_out <= (pulse_width == 3'h7) ? 0 : enable_in;
        end
      end
    end
  end

  // syncronize enalbe_in and generate resync for slave

  always @(posedge clk) begin
    sync_in_d <= sync_in;
    if(device_type == 1'b1) begin
      enable_synced <= enable_in;
      resync <= 1'b0;
    end else begin
      if (~sync_in_d & sync_in) begin
        enable_synced <= enable_in;
        resync <= 1'b1;
      end else begin
        resync <= 1'b0;
      end
    end
  end

endmodule