####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_ad9361

M_DEPS += ../common/ad_addsub.v
M_DEPS += ../common/ad_datafmt.v
M_DEPS += ../common/ad_dcfilter.v
M_DEPS += ../common/ad_dds.v
M_DEPS += ../common/ad_dds_1.v
M_DEPS += ../common/ad_dds_sine.v
M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_pps_receiver.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_tdd_control.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v
M_DEPS += ../common/up_clock_mon.v
M_DEPS += ../common/up_dac_channel.v
M_DEPS += ../common/up_dac_common.v
M_DEPS += ../common/up_delay_cntrl.v
M_DEPS += ../common/up_tdd_cntrl.v
M_DEPS += ../common/up_xfer_cntrl.v
M_DEPS += ../common/up_xfer_status.v
M_DEPS += ../xilinx/common/ad_data_clk.v
M_DEPS += ../xilinx/common/ad_data_in.v
M_DEPS += ../xilinx/common/ad_data_out.v
M_DEPS += ../xilinx/common/ad_mul.v
M_DEPS += ../xilinx/common/ad_rst_constr.xdc
M_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
M_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
M_DEPS += axi_ad9361.v
M_DEPS += axi_ad9361_constr.xdc
M_DEPS += axi_ad9361_ip.tcl
M_DEPS += axi_ad9361_rx.v
M_DEPS += axi_ad9361_rx_channel.v
M_DEPS += axi_ad9361_rx_pnmon.v
M_DEPS += axi_ad9361_tdd.v
M_DEPS += axi_ad9361_tdd_if.v
M_DEPS += axi_ad9361_tx.v
M_DEPS += axi_ad9361_tx_channel.v
M_DEPS += xilinx/axi_ad9361_cmos_if.v
M_DEPS += xilinx/axi_ad9361_lvds_if.v

include ../scripts/library.mk