####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_spi_engine

GENERIC_DEPS += ../../common/ad_rst.v
GENERIC_DEPS += ../../common/up_axi.v
GENERIC_DEPS += axi_spi_engine.v

XILINX_DEPS += ../../common/ad_rst.v
XILINX_DEPS += ../../common/up_axi.v
XILINX_DEPS += ../../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += axi_spi_engine_constr.ttcl
XILINX_DEPS += axi_spi_engine_ip.tcl

XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_ctrl_rtl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl.xml
XILINX_DEPS += ../../spi_engine/interfaces/spi_engine_offload_ctrl_rtl.xml

XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_cdc

INTEL_DEPS += ../../common/ad_mem.v
INTEL_DEPS += ../../intel/common/up_rst_constr.sdc
INTEL_DEPS += ../../util_axis_fifo/address_gray.v
INTEL_DEPS += ../../util_axis_fifo/address_gray_pipelined.v
INTEL_DEPS += ../../util_axis_fifo/address_sync.v
INTEL_DEPS += ../../util_axis_fifo/util_axis_fifo.v
INTEL_DEPS += ../../util_cdc/sync_bits.v
INTEL_DEPS += ../../util_cdc/sync_gray.v
INTEL_DEPS += axi_spi_engine_constr.sdc
INTEL_DEPS += axi_spi_engine_hw.tcl

include ../../scripts/library.mk