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`timescale 1ns/1ns

module prcfg_dac(

  clk,

  // control ports
  control,
  status,

  // FIFO interface
  src_dac_en,
  src_dac_ddata,
  src_dac_dunf,
  src_dac_dvalid,

  dst_dac_en,
  dst_dac_ddata,
  dst_dac_dunf,
  dst_dac_dvalid
);

  parameter   CHANNEL_ID    = 0;
  parameter   DATA_WIDTH    = 32;
  parameter   SYMBOL_WIDTH  = 2;

  localparam  RP_ID         = 8'hA2;
  localparam  SYMBOL_CNTR_WIDTH = $clog2(DATA_WIDTH/SYMBOL_WIDTH);
  localparam  NROF_SYMBOLES = DATA_WIDTH/SYMBOL_WIDTH;

  input                               clk;

  input   [31:0]                      control;
  output  [31:0]                      status;

  output                              src_dac_en;
  input   [(DATA_WIDTH-1):0]          src_dac_ddata;
  input                               src_dac_dunf;
  input                               src_dac_dvalid;

  input                               dst_dac_en;
  output  [(DATA_WIDTH-1):0]          dst_dac_ddata;
  output                              dst_dac_dunf;
  output                              dst_dac_dvalid;

  // output register to improve timing
  reg                                 dst_dac_dunf   = 'h0;
  reg     [(DATA_WIDTH-1):0]          dst_dac_ddata  = 'h0;
  reg                                 dst_dac_dvalid = 'h0;
  reg                                 src_dac_en     = 'h0;

  // internal registers
  reg     [ 7:0]                      pn_data        = 'hF2;
  reg     [31:0]                      status         = 'h0;
  reg     [ 3:0]                      mode           = 'h0;

  reg     [(SYMBOL_WIDTH-1):0]        dac_data_buf[(NROF_SYMBOLES-1):0];
  reg     [(SYMBOL_CNTR_WIDTH-1):0]   symbole_counter = 'd0;
  reg     [2:0]                       sample_counter  = 'd0;

  // internal wires
  wire    [(SYMBOL_WIDTH-1):0]        mod_data;
  wire    [15:0]                      dac_data_fltr_i;
  wire    [15:0]                      dac_data_fltr_q;

  wire    [(DATA_WIDTH-1):0]          dac_data_mode0;
  wire    [(DATA_WIDTH-1):0]          dac_data_mode1_2;

  wire                                mod_en;

  // prbs function
  function [ 7:0] pn;
    input [ 7:0] din;
    reg   [ 7:0] dout;
    begin
      dout[7] = din[6];
      dout[6] = din[5];
      dout[5] = din[4];
      dout[4] = din[3];
      dout[3] = din[2];
      dout[2] = din[1];
      dout[1] = din[7] ^ din[4];
      dout[0] = din[6] ^ din[3];
      pn = dout;
    end
  endfunction

  // update control and status registers
  always @(posedge clk) begin
    status <= { 24'h0, RP_ID };
    mode   <= control[ 7:4];
  end

  // prbs generation
  always @(posedge clk) begin
    if(dst_dac_en == 1) begin
      pn_data <= pn(pn_data);
    end
  end

  // symbol wrapper, data is transmitted MSB first
  genvar i;
  generate
    for (i = 0; i < NROF_SYMBOLES; i = i + 1) begin : SYMBOLE_WRAPPER
        // flop the incoming data when it's valid and all the symbols are pushed out
        always @(posedge clk) begin
            if((src_dac_dvalid == 1'b1) && (symbole_counter == 'd0)) begin
                 dac_data_buf[(NROF_SYMBOLES-i-1)] <= src_dac_ddata[((i+1)*SYMBOL_WIDTH)-1:(i*SYMBOL_WIDTH)];
            end
        end
    end
  endgenerate

  // increment to counter for the symbol mux
  always @(posedge clk) begin
    if((src_dac_dvalid == 1'b1) && (dst_dac_en == 1'b1)) begin
      if(mod_en == 1'b1) begin
        symbole_counter <= symbole_counter + 1;
      end
      sample_counter <= sample_counter + 1;
    end
  end

  // the modulator generate eight samples from each symbol
  // to prevent data loss, need to keep each symbol at data_input port for 8 samples
  assign mod_en = (sample_counter == 7) ? 1'b1 : 1'b0;

  // data for the modulator (prbs or dma)
  assign mod_data = (mode == 1) ? pn_data[ 1:0] : dac_data_buf[symbole_counter];

  // qpsk modulator
  qpsk_mod i_qpsk_mod (
    .clk(clk),
    .data_input(mod_data),
    .data_valid(dst_dac_en),
    .data_qpsk_i(dac_data_fltr_i),
    .data_qpsk_q(dac_data_fltr_q)
  );

  // pass through mode
  assign dac_data_mode0 = src_dac_ddata;
  // modulated data
  assign dac_data_mode1_2 = { dac_data_fltr_q, dac_data_fltr_i };

  // output logic
  always @(posedge clk) begin
    src_dac_en      <= (& symbole_counter) & (& sample_counter);
    dst_dac_dunf    <= (mode == 1) ? 1'b0 : src_dac_dunf;
    dst_dac_ddata   <= (mode == 0) ? dac_data_mode0 : dac_data_mode1_2;
    dst_dac_dvalid  <= (mode == 0) ? src_dac_dvalid  : ((dst_dac_en == 1'b1) ? 1'b1 : 1'b0);
  end

endmodule