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`timescale 1ns/100ps

module axi_ad7616_control (

  // control signals

  reset_n,
  cnvst,
  busy,
  seq_en,
  hw_rngsel,
  chsel,
  crcen,
  ser1w_n,
  burst,
  os,

  end_of_conv,

  // bus interface

  up_rstn,
  up_clk,
  up_wreq,
  up_waddr,
  up_wdata,
  up_wack,
  up_rreq,
  up_raddr,
  up_rdata,
  up_rack

);

  parameter   ID = 0;
  parameter   OP_MODE = 0;

  localparam  PCORE_VERSION = 'h0001001;
  localparam  SW = 0;
  localparam  HW = 1;

  input           clk;
  input           rst;

  output          reset_n;
  output          cnvst;
  input           busy;
  output          seq_en;
  output  [ 1:0]  hw_rngsel;
  output  [ 2:0]  chsel;
  output          crcen;
  output          ser1w_n;
  output          burst;
  output  [ 2:0]  os;

  output          end_of_conv;

  // bus interface

  input           up_rstn;
  input           up_clk;
  input           up_wreq;
  input   [13:0]  up_waddr;
  input   [31:0]  up_wdata;
  output          up_wack;
  input           up_rreq;
  input   [13:0]  up_raddr;
  output  [31:0]  up_rdata;
  output          up_rack;

  // internal signals

  reg     [31:0]  up_scratch = 'b0;
  reg             up_resetn = 'b0;
  reg             up_cnvst_en = 'b0;
  reg             up_ser1w = 'b0;
  reg     [ 7:0]  up_cnvst_high = 'b0;
  reg     [31:0]  up_conv_rate = 'b0;
  reg     [31:0]  cnvst_counter = 32'b0;
  reg     [ 7:0]  pulse_counter = 8'b0;
  reg             cnvst_buf = 1'b0;

  // decode block select


  // processor write interface

  always @(negedge up_rstn or posedge up_clk) begin
    if (up_rstn == 0) begin
      up_wack <= 1'h0;
      up_scratch <= 32'b0;
      up_resetn <= 1'b0;
      up_cnvst_en <= 1'b0;
      up_ser1w <= 1'b0;
      up_cnvst_high <= 8'b0;
      up_conv_rate <= 32'b0;
    end else begin
      up_wack <= up_wreq_s;
      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
        up_scratch <= up_wdata;
      end
      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
        up_resetn <= up_wdata[0];
        up_cnvst_en <= up_wdata[1];
        up_ser1w <= up_wdata[2];
      end
      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h11)) begin
        up_cnvst_high <= up_wdata[7:0];
      end
      if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h12)) begin
        up_conv_rate <= up_wdata;
      end
    end
  end

  // processor read interface

  always @(negedge up_rstn or posedge up_clk) begin
    if (up_rstn == 0) begin
      up_rack <= 1'b0;
      up_rdata <= 32'b0;
    end else begin
      up_rack <= up_rreq_s;
      if (up_rreq_s == 1'b1) begin
        case (up_raddr[7:0])
            8'h00 : up_rdata = PCORE_VERSION;
            8'h01 : up_rdata = ID;
            8'h02 : up_rdata = up_scratch;
            8'h10 : up_rdata = {28'b0, up_ser1w, up_cnvst_en, up_resetn};
            8'h11 : up_rdata = {24'b0, up_cnvst_high};
            8'h12 : up_rdata = up_conv_rate;
        endcase
      end
    end
  end

  // instantiations

  ad_edge_detect #(
    .EDGE(NEG_EDGE)
  ) i_ad_edge_detect (
    .clk (up_clk),
    .rstn (up_rstn),
    .in (busy),
    .out (end_of_conv)
  );

  // convertion start generator
  // NOTE: The minimum convertion cycle is 1 us and the
  //       minimum CNVST high pulse width is 20 ns.
  //       See the AD7616 datasheet for more information.

  always @(posedge clk) begin
    if(up_resetn == 0) begin
      cnvst_counter <= 32'b0;
    end else begin
      cnvst_counter <= (cnvst_counter < up_conv_rate) ? cnvst_counter + 1 : 32'b0;
    end
  end

  always @(cnvst_counter) begin
    cnvst_pulse <= (cnvst_counter == up_conv_rate) ? 1'b1 : 1'b0;
  end

  always @(posedge clk) begin
    if(up_resetn == 1'b0) begin
      pulse_counter <= 8'b0;
      cnvst_buf <= 1'b0;
    end else begin
      pulse_counter <= (cnvst == 1'b1) ? pulse_counter + 1 : 8'b0;
      if(cnvst_pulse == 1'b1) begin
        cnvst_buf <= 1'b1;
      end else if (pulse_counter == up_cnvst_high) begin
        cnvst_buf <= 1'b0;
      end
    end
  end

  assign cnvst <= (up_cnvst_en == 1'b1) ? cnvst_buf : 1'b0;

  // output logic

  assign reset_n = up_resetn;       // device's reset
  assign ser1w_n = ~up_ser1w;       // serial output operates over SDOA and SDOB OR just SDOA

  generate if (OP_MODE == SW) begin

    // ground all the unused control signals

    assign seq_en = 1'b0;
    assign hw_rngsel = 2'b0;
    assign chsel = 3'b0;
    assign crcen = 1'b0;
    assign burst = 1'b0;
    assign os = 3'b0;

  end
  endgenerate

endmodule