// ***************************************************************************
// ***************************************************************************
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// ***************************************************************************

`timescale 1ns/100ps

module fmcadc5_psync (

  up_rstn,
  up_clk,

  psync_0,
  psync_1);

  // 4 wire

  input           up_rstn;
  input           up_clk;
  output          psync_0;
  output          psync_1;

  // internal registers

  reg     [ 7:0]  psync_count = 'd0;
  reg             psync_0 = 'd0;
  reg             psync_1 = 'd0;

  // ~602K

  always @(posedge up_clk or negedge up_rstn) begin
    if (up_rstn == 1'b0) begin
      psync_count <= 7'd0;
      psync_0 <= 1'b0;
      psync_1 <= 1'b1;
    end else begin
      if (psync_count >= 7'h52) begin
        psync_count <= 7'd0;
      end else begin
        psync_count <= psync_count + 1'b1;
      end
      if (psync_count >= 7'h4f) begin
        psync_0 <= ~psync_0;
        psync_1 <= ~psync_1;
      end
    end
  end

endmodule

// ***************************************************************************
// ***************************************************************************