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`timescale 1ns/1ns

module prcfg_dac(

  clk,

  // control ports
  control,
  status,

  // FIFO interface
  src_dac_drd,
  src_dac_ddata,
  src_dac_dunf,

  dst_dac_drd,
  dst_dac_ddata,
  dst_dac_dunf
);

  localparam  RP_ID       = 8'hA2;
  parameter   CHANNEL_ID  = 0;

  input             clk;

  input   [31:0]    control;
  output  [31:0]    status;

  output            src_dac_drd;
  input   [31:0]    src_dac_ddata;
  input             src_dac_dunf;

  input             dst_dac_drd;
  output  [31:0]    dst_dac_ddata;
  output            dst_dac_dunf;

  reg               dst_dac_dunf   = 0;
  reg     [31:0]    dst_dac_ddata  = 0;
  reg               dst_dac_dvalid = 0;
  reg               src_dac_drd    = 0;

  reg     [ 7:0]    pn_data        = 8'hF2;
  reg     [31:0]    status         = 0;

  wire    [ 1:0]    dac_data;
  wire    [15:0]    dac_data_fltr_i;
  wire    [15:0]    dac_data_fltr_q;

  wire    [ 3:0]    mode;

  wire    [31:0]    dac_data_mode0;
  wire    [31:0]    dac_data_mode1_2;

  // prbs function
  function [ 7:0] pn;
    input [ 7:0] din;
    reg   [ 7:0] dout;
    begin
      dout[7] = din[6];
      dout[6] = din[5];
      dout[5] = din[4];
      dout[4] = din[3];
      dout[3] = din[2];
      dout[2] = din[1];
      dout[1] = din[7] ^ din[4];
      dout[0] = din[6] ^ din[3];
      pn = dout;
    end
  endfunction

  always @(posedge clk) begin
    status <= { 24'h0, RP_ID };
  end
  assign mode   = control[ 7:4];

  // pass through mode
  assign dac_data_mode0 = src_dac_ddata;

  // prbs geenration
  always @(posedge clk) begin
    if(dst_dac_drd == 1) begin
      pn_data = pn(pn_data);
    end
  end

  // data source for the modulator
  assign dac_data = (mode == 1) ? pn_data[ 1:0] : src_dac_ddata[ 1:0];

  // modulated data
  assign dac_data_mode1_2 = { dac_data_fltr_q, dac_data_fltr_i };

  // qpsk modulator
  qpsk_mod i_qpsk_mod (
    .clk(clk),
    .data_input(dac_data),
    .data_valid(dst_dac_drd),
    .data_qpsk_i(dac_data_fltr_i),
    .data_qpsk_q(dac_data_fltr_q)
  );

  // output logic for tx side
  always @(posedge clk) begin
    src_dac_drd   <= (mode == 1) ? 1'b0 : dst_dac_drd;
    dst_dac_dunf  <= (mode == 1) ? 1'b0 : src_dac_dunf;
    dst_dac_ddata <= (mode == 0) ? dac_data_mode0 : dac_data_mode1_2;
  end

endmodule