// ***************************************************************************
// ***************************************************************************
// Copyright 2014(c) Analog Devices, Inc.
//
// All rights reserved.
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// are permitted provided that the following conditions are met:
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//       of one or more patent holders.  This license does not release you
//       from the requirement that you obtain separate licenses from these
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//     - Use of the software either in source or binary form, must be run
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// ***************************************************************************
// ***************************************************************************

`timescale 1ns/100ps

module ad_lvds_in (

  // data interface

  rx_clk,
  rx_data_in_p,
  rx_data_in_n,
  rx_data_p,
  rx_data_n,

  // delay-data interface

  up_clk,
  up_dld,
  up_dwdata,
  up_drdata,

  // delay-cntrl interface

  delay_clk,
  delay_rst,
  delay_locked);

  // parameters

  parameter   SINGLE_ENDED = 0;
  parameter   DEVICE_TYPE = 0;
  parameter   IODELAY_CTRL = 0;
  parameter   IODELAY_GROUP = "dev_if_delay_group";

  // data interface

  input               rx_clk;
  input               rx_data_in_p;
  input               rx_data_in_n;
  output              rx_data_p;
  output              rx_data_n;

  // delay-data interface

  input               up_clk;
  input               up_dld;
  input       [ 4:0]  up_dwdata;
  output      [ 4:0]  up_drdata;

  // delay-cntrl interface

  input               delay_clk;
  input               delay_rst;
  output              delay_locked;

  // defaults

  assign up_drdata = 5'd0;
  assign delay_locked = 1'b1;

  // instantiations

  alt_lvds_in i_rx_data_iddr (
    .ck (rx_clk),
    .pad_in (rx_data_in_p),
    .pad_in_b (rx_data_in_n),
    .dout ({rx_data_p, rx_data_n}));

endmodule

// ***************************************************************************
// ***************************************************************************