####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_dmac

GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += 2d_transfer.v
GENERIC_DEPS += address_generator.v
GENERIC_DEPS += axi_dmac.v
GENERIC_DEPS += axi_dmac_regmap.v
GENERIC_DEPS += axi_dmac_regmap_request.v
GENERIC_DEPS += axi_register_slice.v
GENERIC_DEPS += data_mover.v
GENERIC_DEPS += dest_axi_mm.v
GENERIC_DEPS += dest_axi_stream.v
GENERIC_DEPS += dest_fifo_inf.v
GENERIC_DEPS += inc_id.h
GENERIC_DEPS += request_arb.v
GENERIC_DEPS += request_generator.v
GENERIC_DEPS += resp.h
GENERIC_DEPS += response_generator.v
GENERIC_DEPS += response_handler.v
GENERIC_DEPS += splitter.v
GENERIC_DEPS += src_axi_mm.v
GENERIC_DEPS += src_axi_stream.v
GENERIC_DEPS += src_fifo_inf.v

XILINX_DEPS += axi_dmac_constr.ttcl
XILINX_DEPS += axi_dmac_ip.tcl
XILINX_DEPS += bd/bd.tcl

XILINX_DEPS += ../interfaces/fifo_rd.xml
XILINX_DEPS += ../interfaces/fifo_rd_rtl.xml
XILINX_DEPS += ../interfaces/fifo_wr.xml
XILINX_DEPS += ../interfaces/fifo_wr_rtl.xml

XILINX_LIB_DEPS += util_axis_fifo
XILINX_LIB_DEPS += util_axis_resize
XILINX_LIB_DEPS += util_cdc

ALTERA_DEPS += ../common/ad_mem.v
ALTERA_DEPS += ../util_axis_fifo/address_gray.v
ALTERA_DEPS += ../util_axis_fifo/address_gray_pipelined.v
ALTERA_DEPS += ../util_axis_fifo/address_sync.v
ALTERA_DEPS += ../util_axis_fifo/util_axis_fifo.v
ALTERA_DEPS += ../util_axis_resize/util_axis_resize.v
ALTERA_DEPS += ../util_cdc/sync_bits.v
ALTERA_DEPS += ../util_cdc/sync_gray.v
ALTERA_DEPS += axi_dmac_constr.sdc
ALTERA_DEPS += axi_dmac_hw.tcl

include ../scripts/library.mk