####################################################################################
## Copyright 2018(c) Analog Devices, Inc.
## Auto-generated, do not modify!
####################################################################################

LIBRARY_NAME := axi_ad9152

GENERIC_DEPS += ../common/ad_dds.v
GENERIC_DEPS += ../common/ad_dds_1.v
GENERIC_DEPS += ../common/ad_dds_sine.v
GENERIC_DEPS += ../common/ad_rst.v
GENERIC_DEPS += ../common/up_axi.v
GENERIC_DEPS += ../common/up_clock_mon.v
GENERIC_DEPS += ../common/up_dac_channel.v
GENERIC_DEPS += ../common/up_dac_common.v
GENERIC_DEPS += ../common/up_xfer_cntrl.v
GENERIC_DEPS += ../common/up_xfer_status.v
GENERIC_DEPS += axi_ad9152.v
GENERIC_DEPS += axi_ad9152_channel.v
GENERIC_DEPS += axi_ad9152_core.v
GENERIC_DEPS += axi_ad9152_if.v

XILINX_DEPS += ../xilinx/common/ad_mul.v
XILINX_DEPS += ../xilinx/common/ad_rst_constr.xdc
XILINX_DEPS += ../xilinx/common/up_clock_mon_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_cntrl_constr.xdc
XILINX_DEPS += ../xilinx/common/up_xfer_status_constr.xdc
XILINX_DEPS += axi_ad9152_ip.tcl

ALTERA_DEPS += ../altera/common/ad_mul.v
ALTERA_DEPS += ../altera/common/up_clock_mon_constr.sdc
ALTERA_DEPS += ../altera/common/up_rst_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_cntrl_constr.sdc
ALTERA_DEPS += ../altera/common/up_xfer_status_constr.sdc
ALTERA_DEPS += axi_ad9152_hw.tcl

include ../scripts/library.mk