pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Adrian Costina	4bda0c3a1a	cftl_cip: ip automatic version update	2017-04-14 16:54:07 +03:00
Istvan Csomortani	81a1c21553	util_pmod_adc: Reset line changed to active low reset.	2015-09-30 12:33:46 +03:00
Istvan Csomortani	5f12c8c7d4	cftl_cip/common: Fix parameter names for dmac	2015-09-30 12:32:48 +03:00
Lars-Peter Clausen	6d87f537da	cftl_cip: Drop explicit axi_dmac clock synchronicity configuration The axi_dmac core is now capable of detecting whether its different parts run in different clock domains or not. No need to configure it manually any more. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2015-09-18 15:27:49 +02:00
Istvan Csomortani	d52308f074	axi_dmac: Change parameter name 2D_TRANSFER Parameter name can't start with numbers, 2D_TRANSFER was changed to DMA_2D_TRANSFER	2015-08-20 10:14:22 +03:00
Istvan Csomortani	57cfb7cfb1	hdl/library: Update the IP parameters The following IP parameters were renamed: PCORE_ID --> ID PCORE_DEVTYPE --> DEVICE_TYPE PCORE_IODELAY_GROUP --> IO_DELAY_GROUP CH_DW --> CHANNEL_DATA_WIDTH CH_CNT --> NUM_OF_CHANNELS PCORE_BUFTYPE --> DEVICE_TYPE PCORE_ADC_DP_DISABLE --> ADC_DATAPATH_DISABLE CHID --> CHANNEL_ID PCORE_DEVICE_TYPE --> DEVICE_TYPE PCORE_MMCM_BUFIO_N --> MMCM_BUFIO_N PCORE_SERDES_DDR_N --> SERDES_DDR_N PCORE_DAC_DP_DISABLE --> DAC_DATAPATH_DISABLE DP_DISABLE --> DATAPATH_DISABLE PCORE_DAC_IODELAY_ENABLE --> DAC_IODELAY_ENABLE C_BIG_ENDIAN --> BIG_ENDIAN C_M_DATA_WIDTH --> MASTER_DATA_WIDTH C_S_DATA_WIDTH --> SLAVE_DATA_WIDTH NUM_CHANNELS --> NUM_OF_CHANNELS CHANNELS --> NUM_OF_CHANNELS PCORE_4L_2L_N -->QUAD_OR_DUAL_N C_ADDRESS_WIDTH --> ADDRESS_WIDTH C_DATA_WIDTH --> DATA_WIDTH C_CLKS_ASYNC --> CLKS_ASYNC PCORE_QUAD_DUAL_N --> QUAD_DUAL_N NUM_CS --> NUM_OF_CS PCORE_DAC_CHANNEL_ID --> DAC_CHANNEL_ID PCORE_ADC_CHANNEL_ID --> ADC_CHANNEL_ID PCORE_CLK0_DIV --> CLK0_DIV PCORE_CLK1_DIV --> CLK1_DIV PCORE_CLKIN_PERIOD --> CLKIN_PERIOD PCORE_VCO_DIV --> VCO_DIV PCORE_Cr_Cb_N --> CR_CB_N PCORE_VCO_MUL --> VCO_MUL PCORE_EMBEDDED_SYNC --> EMBEDDED_SYNC PCORE_AXI_ID_WIDTH --> AXI_ID_WIDTH PCORE_ADDR_WIDTH --> ADDRESS_WIDTH DADATA_WIDTH --> DATA_WIDTH NUM_OF_NUM_OF_CHANNEL --> NUM_OF_CHANNELS DEBOUNCER_LEN --> DEBOUNCER_LENGTH ADDR_WIDTH --> ADDRESS_WIDTH C_S_AXIS_REGISTERED --> S_AXIS_REGISTERED Cr_Cb_N --> CR_CB_N ADDATA_WIDTH --> ADC_DATA_WIDTH BUFTYPE --> DEVICE_TYPE NUM_BITS --> NUM_OF_BITS WIDTH_A --> A_DATA_WIDTH WIDTH_B --> B_DATA_WIDTH CH_OCNT --> NUM_OF_CHANNELS_O M_CNT --> NUM_OF_CHANNELS_M P_CNT --> NUM_OF_CHANNELS_P CH_ICNT --> NUM_OF_CHANNELS_I CH_MCNT --> NUM_OF_CHANNELS_M 4L_2L_N --> QUAD_OR_DUAL_N SPI_CLK_ASYNC --> ASYNC_SPI_CLK MMCM_BUFIO_N --> MMCM_OR_BUFIO_N SERDES_DDR_N --> SERDES_OR_DDR_N CLK_ASYNC --> ASYNC_CLK CLKS_ASYNC --> ASYNC_CLK SERDES --> SERDES_OR_DDR_N GTH_GTX_N --> GTH_OR_GTX_N IF_TYPE --> DDR_OR_SDR_N PARALLEL_WIDTH --> DATA_WIDTH ADD_SUB --> ADD_OR_SUB_N A_WIDTH --> A_DATA_WIDTH CONST_VALUE --> B_DATA_VALUE IO_BASEADDR --> BASE_ADDRESS IO_WIDTH --> DATA_WIDTH QUAD_DUAL_N --> QUAD_OR_DUAL_N AXI_ADDRLIMIT --> AXI_ADDRESS_LIMIT ADDRESS_A_DATA_WIDTH --> A_ADDRESS_WIDTH ADDRESS_B_DATA_WIDTH --> B_ADDRESS_WIDTH MODE_OF_ENABLE --> CONTROL_TYPE CONTROL_TYPE --> LEVEL_OR_PULSE_N IQSEL --> Q_OR_I_N MMCM --> MMCM_OR_BUFR_N	2015-08-19 14:11:47 +03:00
Adrian Costina	90a5bb81b6	cftl_cip: Updated project to work with the new util_pmod_adc core	2015-05-05 23:34:52 +03:00
Istvan Csomortani	0162009099	cftl_cip: Update project to the new frame work.	2015-04-02 15:14:04 +03:00
Istvan Csomortani	1613f7fb41	cftl_cip: Add util_pmod_fmeter IP to library Frequency meter IP for CN0332.	2015-02-23 17:20:12 +02:00
Istvan Csomortani	3113abf038	cftl_cip: Add gpio counter for CN0332 Add a counter core to the design, to support the CN0332 pmod with a speed sensor. Change a naming for the custom cores.	2015-02-18 18:24:46 +02:00
Istvan Csomortani	2d607d765b	cftl_cip: Add a clock input to the device core, for the SPI clock. This clock can be adjustable from the system_project.tcl	2015-02-04 14:55:17 +02:00
Istvan Csomortani	659e0cca4e	cftl_cip: Initial check in. Project cftl_cip supports the following Circuits from the Lab pmods: + EVAL-CN0350-PMDZ + EVAL-CN0335-PMDZ + EVAL-CN0336-PMDZ + EVAL-CN0337-PMDZ Note: Additional testing needed!	2015-01-23 18:29:32 +02:00

12 Commits (ff50963c7f839e7776655101b088742a43c7eb66)