Commit Graph

51 Commits (ff50963c7f839e7776655101b088742a43c7eb66)

Author SHA1 Message Date
Istvan Csomortani 6ebef5dde0 make: Update make files 2017-06-26 15:51:19 +01:00
Rejeesh Kutty dd48929327 hdlmake.pl - updates 2017-06-06 12:25:35 -04:00
Rejeesh Kutty f278b6e6c9 adrv9371x/a10soc- constraints/project updates 2017-06-06 12:23:26 -04:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Istvan Csomortani 4c998d1e18 make: Update make files 2017-05-25 15:12:17 +03:00
Lars-Peter Clausen 01aea161fa Create CDC helper library
Move the CDC helper modules to a dedicated helper modules. This makes it
possible to reference them without having to use file paths that go outside
of the referencing project's directory.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Rejeesh Kutty ff7dc41066 alt-jesd- constraints update 2017-05-18 09:55:24 -04:00
Rejeesh Kutty f8f7bdd6a6 a10soc- fix version check 2017-05-17 16:26:28 -04:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani ef97c1e375 adrv9371x/a10soc: Fix constraints
Signed-off-by: Istvan Csomortani <istvan.csomortani@analog.com>
2017-05-02 14:37:11 +03:00
Rejeesh Kutty b3ce821311 change pl ddr clock to 1G 2017-05-01 09:35:10 -04:00
Rejeesh Kutty cfd4e006b3 hdlmake updates 2017-04-25 15:46:26 -04:00
Istvan Csomortani 6ed721ee66 adrv9371/a10soc: Integrate the avl_dacfifo into project 2017-04-21 13:27:35 +03:00
Adrian Costina 942d69a30c Makefiles: Change MMU enabling parameter for altera designs from MMU to NIOS2_MMU 2017-04-18 10:57:16 +03:00
Rejeesh Kutty 8eb1dd0a8b adrv9371x/altera- xilinx/chip-select consistency 2017-03-29 12:59:09 -04:00
Rejeesh Kutty deb8635854 adrv9371x/altera- gpio equivalency fix 2017-03-27 16:37:55 -04:00
Rejeesh Kutty cc6bf53d98 adrv9371x/a10soc- altera reset synchronizer false path? 2017-03-23 09:46:40 -04:00
Rejeesh Kutty 8063ba2b66 make updates 2017-03-20 16:05:18 -04:00
Rejeesh Kutty 3fa9a30f0e a10soc/plddr4- lower mem clk to meet timing 2017-03-06 14:12:25 -05:00
Rejeesh Kutty 936c441763 adrv9371x- dacfifo bypass-gpio control 2017-03-06 10:35:09 -05:00
Rejeesh Kutty bc6a09c828 adrv9371x/a10soc- dacfifo added 2017-03-01 15:35:04 -05:00
AndreiGrozav 0cc5130c9a adrv9371x: Set XCVR Tx/RX clk/data voltage levels at 1V 2017-03-01 11:32:17 +02:00
AndreiGrozav dc168f41fe adrv9371_a10soc: Fixed port assignments 2017-03-01 11:32:17 +02:00
Rejeesh Kutty 4a783d523d projects/altera* - default & common qsys commands 2016-12-20 16:27:44 -05:00
Adrian Costina 8ebc8fe4e2 updated makefiles 2016-12-09 23:06:41 +02:00
Adrian Costina ce3b6a2d3f adrv9371x: Updated constraints for altera projects 2016-11-04 18:20:46 +02:00
Rejeesh Kutty 671a547c2b hdlmake- updates 2016-11-01 12:41:25 -04:00
Rejeesh Kutty f752f0c9d7 a10soc- xcvr updates 2016-10-27 09:25:00 -04:00
Rejeesh Kutty cb97bc500a hdlmake updates 2016-10-17 16:29:57 -04:00
Adrian Costina 143423e3b9 adrv9371x: A10SOC, fix Makefile and system scripts to be compatible with altera 2016-09-21 18:13:02 +03:00
Istvan Csomortani 16ee1336c3 Makefile: Update make files 2016-09-15 11:41:06 +03:00
Adrian Costina 521c41ce32 adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier 2016-09-08 11:44:45 +03:00
Rejeesh Kutty f697490de6 hdlmake- updates 2016-08-19 15:59:41 -04:00
dbogdan 03c83b59bf adrv9371x/a10soc: Export axi_ad9371_s and xcvr_reconfig_avmm 2016-08-17 19:03:53 +03:00
dbogdan 4658686ae1 adrv9371x/a10soc: Misc changes for being able to run Linux 2016-08-16 11:56:25 +03:00
Dragos Bogdan 39c1c83d00 adrv9371x/a10soc: Fix spi_csn assignment 2016-08-12 10:07:11 +03:00
Adrian Costina 0b0aa8e6c0 Makefile: Add MMU option to altera makefiles 2016-08-11 17:46:54 +03:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty eaf4d4a19d makefile updates 2016-06-10 14:26:14 -04:00
Rejeesh Kutty 3351ff607e adrv9371x- need to investigate merge with avalon 2016-06-02 16:22:53 -04:00
Rejeesh Kutty c293c04634 hdl make updates 2016-06-01 13:53:09 -04:00
Rejeesh Kutty 46b464ed72 adrv9371/a10soc- qsys updates 2016-06-01 13:48:51 -04:00
Rejeesh Kutty a958ef27da adrv9371- qsys updates 2016-06-01 13:48:51 -04:00
Rejeesh Kutty 5b2a90ffff adrv9371- qsys 2016-06-01 13:48:51 -04:00
Istvan Csomortani a6fbf6c20b adrv9371x: Update the Makefiles 2016-05-27 14:13:55 +03:00
Rejeesh Kutty 0d1c4d232e a10soc- updates-1 2016-05-20 16:14:57 -04:00
Rejeesh Kutty 09520709b0 make updates 2016-05-20 12:35:45 -04:00