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6 Commits (ff2e1021827f8a4f19b3777ed9dad0e1c1cceb52)

Author SHA1 Message Date
Lars-Peter Clausen ff2e102182 axi_dmac: Add clock signal spec for m_axis/s_axis bus 
This silences warnings from the tools about having no clock assigned to the bus.
Also fix the name of the TVALID signal.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-30 13:18:50 +02:00
Lars-Peter Clausen c927e90ee1 axi_dmac/axi_fifo: Add missing file 
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-09-15 21:04:57 +02:00
Rejeesh Kutty 1396a215e5 library: local constraints 2014-08-14 15:09:47 -04:00
Rejeesh Kutty 56ddce1e8c dmac: create fifo interface to avoid being treated as axi control stream 2014-05-27 10:25:14 -04:00
Lars-Peter Clausen f02ba999ae axi_dmac: Add support for DMA bus widths other than 64 bit 
There were a few place in the core where it assumed a 64-bit wide bus. Make this
configurable using parameters. The patch also adds support for having different
DMA bus widths on the source and destination side.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 2014-03-13 13:20:10 +01:00
Adrian Costina 831c19ea84 Added axi_dmac, axi_fifo and misc files in library 2014-03-06 18:16:02 +02:00