pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Adrian Costina	f43b5d707e	fmcomms2: Reduced clock frequency for ILA to meet timing for ZED Modified ZED constraints to 250 MHz for the clock from AD9361	2014-09-16 16:08:28 -04:00
ATofan	2c898bf3a2	Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project ZC706 runs rx_clk at 250 MHz. ZC702 and ZED run rx_clk at 200 MHz due to slower fabric. The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly. Both DDS and DMA mode work.	2014-03-18 15:27:42 +02:00

Author

SHA1

Message

Date

Adrian Costina

f43b5d707e

fmcomms2: Reduced clock frequency for ILA to meet timing for ZED

Modified ZED constraints to 250 MHz for the clock from AD9361

2014-09-16 16:08:28 -04:00

ATofan

2c898bf3a2

Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project

ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.

2014-03-18 15:27:42 +02:00

2 Commits (fe8a076b2ee24e54edfc0b9f9f5220d452991cc1)