Commit Graph

53 Commits (fca88caf9377ecb6e9e6aec1971bb6b868053434)

Author SHA1 Message Date
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Istvan Csomortani 50cdb6db67 Merge branch 'jesd204' into dev 2017-05-31 20:44:32 +03:00
Istvan Csomortani 84b2ad51e2 license: Add some clarification to the header license 2017-05-31 18:18:56 +03:00
Istvan Csomortani 85ebd3ca01 license: Update license terms in hdl source files
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
Lars-Peter Clausen bbe457acea fmcadc2: Convert to ADI JESD204
Convert the FMCADC2 project to the ADI JESD204 link layer core. The change
is very straight forward, but a matching change on the software side is
required.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-05-23 11:16:07 +02:00
Rejeesh Kutty 0eaa98370e fmcadc2/vc707- spi clock reg can't be on iob 2017-05-19 15:22:33 -04:00
Istvan Csomortani 9055774795 all: Update license for all hdl source files
All the hdl (verilog and vhdl) source files were updated. If a file did not
have any license, it was added into it. Files, which were generated by
a tool (like Matlab) or were took over from other source (like opencores.org),
were unchanged.

New license looks as follows:

Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.

Each core or library found in this collection may have its own licensing terms.
The user should keep this in in mind while exploring these cores.

Redistribution and use in source and binary forms,
with or without modification of this file, are permitted under the terms of either
 (at the option of the user):

  1. The GNU General Public License version 2 as published by the
     Free Software Foundation, which can be found in the top level directory, or at:
https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html

OR

  2.  An ADI specific BSD license as noted in the top level directory, or on-line at:
https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
2017-05-17 11:52:08 +03:00
Istvan Csomortani 1c23cf4621 all: Update verilog files to verilog-2001 2017-04-13 11:59:55 +03:00
Rejeesh Kutty fb4a583613 projects/system_bd- adc/dac fifo board designs 2017-02-27 16:06:39 -05:00
Istvan Csomortani ac2e5a9dac constraints: Update constraints
Xilinx recommends that all synchronizer flip-flops have
their ASYNC_REG property set to true in order to preserve the
synchronizer cells through any logic optimization during synthesis
and implementation.
2017-02-24 13:43:32 +02:00
Rejeesh Kutty edd5e9570f file renamed; sed output; fingers crossed 2017-02-22 15:56:37 -05:00
Istvan Csomortani 343d0472d4 fmcadc2: Move GT setting to common/system_bd.tcl 2017-02-16 14:56:25 +02:00
Istvan Csomortani 07184b31d2 fmcadc2: Define default clock selection for Xilinx GTs 2017-02-16 12:35:24 +02:00
Istvan Csomortani 1156aeac16 ad_sysref_gen: Update SYSREF related constraints 2016-12-19 18:07:05 +02:00
Istvan Csomortani 0c42e04bc3 fmcadc2: Integrate ad_sysref_gen into the project 2016-12-19 12:16:05 +00:00
AndreiGrozav c455d2d64f fmcadc2/vc707: Disabele axi_spi constraint file
The interface ports of the AXI SPI IP are not connected
  directly to a IOBUF, this results in a CRITICAL WARNING
2016-12-13 19:15:44 +02:00
AndreiGrozav 3dceb53984 fmcadc2/vc707: Fix timing violations 2016-12-08 19:51:18 +02:00
AndreiGrozav 8eaae98728 fmcadc2: Updates 2016-12-07 21:43:19 +02:00
Rejeesh Kutty 170c781d02 hdlmake.pl- updates 2016-12-01 13:52:11 -05:00
AndreiGrozav aff45eae5f fmcadc2: xcvr updates 2016-11-21 18:45:38 +02:00
AndreiGrozav 93fa5aeec3 fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2 2016-09-01 16:11:39 +03:00
Rejeesh Kutty ce1fed1ce6 dmafifo- adc/dac split 2016-08-16 12:54:39 -04:00
Istvan Csomortani 0cd608a7e2 lib_refactoring: Update Make files 2016-08-08 16:38:38 +03:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina d60bce654c Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools 2016-08-05 15:16:04 +03:00
Rejeesh Kutty e42b4ea378 hdlmake- updates 2016-08-04 13:28:25 -04:00
Istvan Csomortani 7ca8e10004 make: Update Make files 2016-08-01 14:24:48 +03:00
AndreiGrozav be74db656c ad6674evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1:
Update system_project.tcl scripts to correctly select the necessary
constraint files
2016-05-04 19:37:33 +03:00
AndreiGrozav 3ca3414522 fmcadc2: Fixed bus data width 2016-05-04 19:20:01 +03:00
AndreiGrozav 9104b2cc60 ad6676evb, fmcadc2, fmcadc4, fmcadc5,...
ad6676evb, fmcadc2, fmcadc4, fmcadc5, fmcjesdadc1: Remove unused
set_proprieties
2016-05-04 19:13:25 +03:00
Rejeesh Kutty 3006c5a223 make updates 2016-04-11 16:14:59 -04:00
Adrian Costina 9cd0378003 fmcadc2: Added clock constraint for the ADC path 2016-01-22 15:44:04 +02:00
Adrian Costina 9d2b8809df Makefiles: Updated Makefiles 2015-10-23 10:44:27 +03:00
Adrian Costina 848b51699c fmcadc2: Updated VC707 project 2015-09-25 17:28:15 +03:00
Adrian Costina a7da779b94 Makefile: Updated Makefiles 2015-07-16 18:19:42 +03:00
Rejeesh Kutty a6cae6b477 iobuf: do is a system verilog keyword 2015-05-21 14:06:17 -04:00
Lars-Peter Clausen 6b9906b22b Refresh Makefiles
Re-generate the Makefiles after a small update to the generation script:
- Entries are sorted alphabetically
- Empty dependency lines are skipped

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-05-21 14:21:54 +02:00
Adrian Costina c19749361d Makefiles: Updated makefiles to have as a result the programming file instead of the project file.
Also fixed altera projects dependencies
2015-05-18 17:22:46 +03:00
Adrian Costina 91279253ef Makefiles: Added mig project file as a dependency for Microblaze based projects. Also updated usdrx1 a5gt Makefile 2015-05-08 15:31:40 +03:00
Adrian Costina 949abcdc8f Makefile: Updated makefiles so that the project recipe does not depend on lib 2015-05-06 14:58:29 +03:00
Istvan Csomortani bb185296d7 fmcadc2_vc707: Increase the BRAM FIFO size to its maximum: it can store 1M samples.
The 2^18 dma address width with a 64 dma data width will result a FIFO, what will be implemented by 512 RAMB36 cells.
This is a the maximum BRAM FIFO depth in case of the VC707.
2015-04-23 18:00:00 +03:00
Adrian Costina a61a195e3f Makefiles: Updated makefiles to add the new constraints as dependecies 2015-04-23 11:16:39 +03:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Istvan Csomortani 8b5d1a8693 fmcadc2: Connect the second CS line for the external SPI interface 2015-04-15 19:08:17 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Rejeesh Kutty 4f7f109056 util_adcfifo: added 2015-04-07 16:08:38 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty ae960e66e9 makefile: added 2015-04-01 16:29:07 -04:00
Rejeesh Kutty 8bc589a4d4 fmcadc2/vc707: 2014.4 updates 2015-03-26 15:07:17 -04:00