Commit Graph

2394 Commits (fbb3a154ff2f11b853d21ab64b03bc8de730d7e6)

Author SHA1 Message Date
Istvan Csomortani e7636f0380 axi_laser_driver: Define up_pulse_s wire in regmap 2019-10-16 15:18:43 +03:00
Istvan Csomortani 5bcaf05355 ad_ss_444to422: localparam can not be used in port definition 2019-10-16 15:18:29 +03:00
Istvan Csomortani b62aab985d ad_csc_RGB2CrYCb: localparam can not be used in port definition 2019-10-16 15:18:29 +03:00
Istvan Csomortani 1b2405a454 ad_csc_CrYCb2RGB: localparam can not be used in port definition 2019-10-16 15:18:29 +03:00
Istvan Csomortani fd74c270c5 adi_ip_xilinx: Add constraint files to constrs_1 fileset 2019-10-03 18:04:34 +03:00
Arpadi 5b79df1aa8 sys_id: version fix 2019-10-03 17:30:18 +03:00
Istvan Csomortani 97d4a14e2b util_cpack2_hw.tcl: Define allowed ranges for NUM_OF_CHANNELS
The number of channels must be round up to the closest next power of
two.
2019-10-02 15:32:17 +03:00
Istvan Csomortani acba490c2e ad_ip_jesd204_tpl_adc: BITS_PER_SAMPLE is a HDL parameter 2019-10-02 15:32:17 +03:00
Istvan Csomortani a49138c257 axi_laser_driver: Add support for Intel platforms 2019-10-02 15:32:17 +03:00
Istvan Csomortani 103cbe73dc intel/adi_jesd204: Add support for external core clock
In Subclass 1 mode, we need to use a separate clock (device clock) to
drive the link and transport layer of the interface. Implement the
required infrastructure for this scenario.

The clock domain crossing will be done in by the TX|RX_FIFO in the PCS.
2019-10-02 15:32:17 +03:00
Istvan Csomortani aeaefd2c1c intel/jesd204_phy: Add support for external coreclkin
In Subclass 1 mode an external device clock (core clock) is used,
instead of the PCS output clock, to drive the link and transport layer.

Define an additional parameter, which can be used to enable clock input
port for the PHY module, which can be used as rx|tx_coreclkin source.
2019-10-02 15:32:17 +03:00
Istvan Csomortani 20dd17aa07 util_cpack2: Update hw.tcl file 2019-10-02 15:32:17 +03:00
StancaPop 9c9ce928d8
Merge pull request #346 from analogdevicesinc/spi_engine_trigger_update
spi_engine: Update pulse generation
2019-10-02 14:42:41 +03:00
AndreiGrozav e45f014138 intel/axi_adxcvr_up: Add device spec register 2019-10-02 08:39:01 +03:00
Laszlo Nagy 83d3bded63 axi_ad9361:xilinx:axi_ad9361_lvds_if: fix Rx latency
This commit reverts part of the changes done in the following commit:

- ff50963c7f -
"axi_ad9361- altera/xilinx reconcile- may be broken- do not use"

The above mentioned commit introduced latency variations on the Rx path
at different sample rates, or within the same sample rate after sample
rate changes. The variation is caused by multiple positions of the frame
detection combined with a free running toggle (rx_valid) that is not synchronized
with the actual samples.

Having a single frame detection position eliminates the latency
variation.
2019-09-27 17:52:10 +03:00
Laszlo Nagy 1d7a621567 axi_ad9361: make the use of Rx SSI clock optional
When having multiple 936x in parallel, this change enables the use of source
synchronous received clock from the master as sampling clock for other slaves.
This will eliminate skew between the interfaces since the data delays
are going to be tuned against the master clock after a multi-chip
synchronization (MCS) is done. This eliminates the clock crossing from
the slave to master domain inside the FPGA.
2019-09-27 17:52:10 +03:00
Laszlo Nagy cdaaa49a2a axi_ad9361: sync dac_valid to adc_valid
Sync the two valid signals to keep a fixed phase relationship between
the Rx ant Tx channels, this way avoiding +/- 1 sample differences
on the Tx-Rx latency between consecutive transfers.
2019-09-27 17:52:10 +03:00
Stanca Pop 164aa97ec3 spi_engine: Update pulse generation
The pulse period had a fixed value. Therefore, in order to be able
to configure it from the software, a 32b register pulse_period_reg
was added in axi_spi_engine. Also, to generate the pulse, the
output register pulse_gen_loadc was added.
2019-09-27 17:02:37 +03:00
AndreiGrozav cfc8ff51e1 axi_adc_trigger: equalize delay paths
- Change the trigger delay path to match between the internal and
external(axi_logic_analyzer delays).
2019-09-13 11:55:11 +03:00
AndreiGrozav f5ac0f7019 axi_logic_analyzer: equalize delay paths
- Add parameter for input data delay time to easily match the one of the
adc_trigger.
- Change the trigger delay path to match between the internal and
external(adc_trigger delays).
2019-09-13 11:55:11 +03:00
Stanca Pop 5ec87615b0 axi_spi_engine: Fix the SYNC interface
The ready signal of the SYNC interface should be always 1'b1,
regardless of ASYNC_SPI_VALUE.

Drive the ready with one in both branches of the ASYNC_SPI_CLK
generate block.
2019-09-11 16:45:30 +03:00
AndreiGrozav a69863609b axi_adc_trigger: Fix trigger out glitches
Currently trigger out pin is hold for 1ms in the next translation(t+1)
state(0 or 1). But not in the state that follows (t+2). This commit
fixes this issue and simplifies the logic.
2019-08-30 14:00:43 +03:00
Istvan Csomortani 97dfb938b6 axi_laser_driver: Fix the up_axi instance 2019-08-29 08:59:56 +03:00
Istvan Csomortani 3cd82c989c ad_3w_spi: Add a 4-wire to 3-wire SPI converter
The module is compliant with the SPI interface specified in ADI-SPI
technical specification.
(https://wiki.analog.com/_media/resources/technical-guides/adispi_rev_1p0_customer.pdf)
2019-08-28 16:13:12 +03:00
Arpadi 63942a6b9b talise_fan_control: updated ip with new fan parameters 2019-08-26 19:01:48 +03:00
Istvan Csomortani aa5fdf903e Makefile: Update makefiles 2019-08-26 16:58:01 +03:00
AndreiGrozav 245f3f9704 axi_dac_interpolate: Fix channel sync mechanism
The previous channel sync mechanism was simply holding the transmission by
pulling down the dma_rd_en of the two DMAs for each channel(set reg 0x50). After a
period of time (that will take the two DMAs to have the data ready to move)
the dma_rd_en was set for both channels, resulting in a synchronized start.
  This mechanism is valid when the two channels are streaming the same
type of data (constant, waveform, buffer or math) at close frequencies.
Streaming 10MHz on a channel and 100KHz on the second one will result
in different interpolation factors being used for the two channels.
  The interpolation counter runs only when the dma_transfer_suspended(reg 0x50)
is cleared. Because of this, different delays are added by the interpolation
counter one DMA with continuous dma_rd_en will have data earlier than the
one with dma_rd_en controlled by the interpolation counter. Furthermore,
because the interpolation counter value is not reset at each
dma_transfer_suspended, the phase shift between the 2 channels will
differ at each start of transmission.

  To make the transfer start synced immune to the above irregularities a
sync_transfer_start register was added (bit 1 of the 0x50 reg).
When this bit is set and the bit 0(dma_transfer_suspended) is toggled,
the interpolation counters are reset. Each channel enables it's DMA until
valid data is received, then it waits for the adjacent channel to get valid data.
This mechanism will be simplified in a future update by using a streaming
interface between the axi_dac_interpolate and the DMAs that does not require
the probing of the DMA.
2019-08-22 18:07:45 +03:00
AndreiGrozav 53f466a93e axi_adc_trigger: Fix low sampling rate external trigger acknoladge
The decimation module controls the valid signal. The whole triggering mechanism
is active only when the valid signal is active.
In the case of low sampling rates, the valid signal is active once every
n clock cycles. If an external trigger condition is fulfilled and the data valid
signal is low at the time, that trigger will be ignored by the DMA.

To solve this issue, the trigger is held high until the valid is asserted.
And it stays high for at least one clock cycle.
2019-08-22 18:06:10 +03:00
AndreiGrozav 3b02a2a6c1 axi_logic_analyzer: Add module cascade support
The trigger signal that goes to the DMA(fifo_wr_sync) does not pass through
the variable fifo, for this reason, a 3 clock cycles delay is required, to
keep in sync the data with the trigger.
On the other hand, to be able to cascade the axi_logic_analyzer with
axi_adc_trigger, there should be small delays on the trigger path, for this
reason the trigger_out_adc was created.

Remove the extra delays on the trigger_i(external trigger pins).
2019-08-22 18:06:10 +03:00
AndreiGrozav 30bdb67994 util_extract: Use less delays in axi_adc_trigger 2019-08-22 18:06:10 +03:00
AndreiGrozav b5dfdcfb84 axi_adc_trigger: Add cascade support.
- Add embedded trigger as an option. The use of the embedded trigger as an
option in the data stream is done for further processing, keeping the data
synchronized with the trigger.
When instrument (module) trigger is desired (logic_analyzer - adc_trigger),
a small propagation time is required, hence the need to remove the
util_extract(trigger extract) module from the data path.

- Add more options for the IO triggering. This will open the door for multiple
M2k synchronization(triggering).
trigger_o mux:
1 - trigger flag (from regmap)
2 - external pin trigger (Ti)
3 - external pin trigger (To)
4 - internal adc trigger
5 - logic analyzer trigger

The signal passed to trigger_o must not be delayed, but the new value has to be
kept for a short period, 1ms (100000 clock cycles), to reduce switch noises in
the system.

The axi_adc_trigger handles 3 output triggers:
- trigger_o - external trigger (1 clock cycle delay)
- trigger_out - signals on dmac/fifo_wr_sync the start of a new transfer.
A variable fifo depth is present in the data path, which delays the data
arriving at the DMA with 3 clock cycles. By coincidence, the external trigger
is synchronized and detected on 3 clock cycles. To get a maximum optimization
the trigger_out will be delayed with 3 clock cycles for internal triggers and
directly forwarded in the case of an external trigger.
- trigger_out_la (cascade trigger for logic_analyzer - m2k example)

Because the trigger_out_la must have a small delay, to get a realible
instrument triggering mechanism, a 1 delay clock cycle must be added on the
trigger paths, to avoid creating a closed combinatorial loop.

Increase pcore version. The major version 3 is used to describe the instrument
trigger updates.
2019-08-22 18:06:10 +03:00
Arpadi baacc906a6 ad7616_bugfix: read data multiplexation 2019-08-22 17:59:00 +03:00
Nick Pillitteri b77f922de0 axi_generic_adc: infer clock for input adc_clk 2019-08-22 10:39:59 +03:00
AndreiGrozav 36a1767329 Add generic fir filters processes for RF projects 2019-08-20 16:24:47 +03:00
Laszlo Nagy 7f72340be8 axi_dmac: fix timing constraints
When source clock is asynchronous to request clock the rewind request
handshake block must be constrained based on request clock domain.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 056c43dc98 axi_laser_driver: Set default value for sequencer offset 2019-08-08 14:26:07 +03:00
Istvan Csomortani d43e6ee239 axi_laser_driver: TIA's are controlled individually in manual mode
Update the sequencer, so the TIA channel selection can be controlled separately
for each TIA, when the sequencer runs in manual mode.
2019-08-08 14:26:07 +03:00
Istvan Csomortani d096b8f6f4 ad_fmclidar1_ebz: Move the util_axis_syncgen into common direcotry 2019-08-08 14:26:07 +03:00
Istvan Csomortani 21bbc900c8 ad_fmclidar1_ebz: Initial commit
This commit was created by squashing the following commits, these
messages were kept just for sake of history:

  ad9694_500ebz: Mirror the SPI interface to FMCB
  ad9694_500ebz: Set transceiver reference clock to 250
  ad9694_500ebz: Allow to configure number of lanes, number of converters
                 and sample rate
  axi_ad9694: Fix number of lanes, it must be 2
  ad9694_500ebz: Update the mirrored spi pin assignments
  ad9694_500ebz: Gate SPI MISO signals based on chip-select
  ad9694_500ebz: Set channel pack sample width
  ad9694_500ebz: Change reference clock location
  ad9694_500ebz: Remove transceiver memory map arbitration
  ad9694_500ebz: Ensure ADC FIFO DMA_DATA_WIDTH is not larger ADC_DATA_WIDTH
  ad9694_500ebz: Adjust breakout board pin locations
  ad_fmclidar1_ebz: Rename the ad9694_500ebz project
  ad_fmclidar1_ebz: Fix lane mapping
  ad_fmclidar1_ebz: Delete deprecated files
  ad_fmclidar1_ebz: Integrate the axi_laser_driver into the design
  ad_fmclidar1_ebz: OTW is an active low signal
  ad_fmclidar1_ebz: zc706: Fix iic_dac signals assignment
  ad_fmclidar1_ebz: Switch to util_adcfifo
  ad_fmclidar1_ebz: Enable synced capture for the fifo
  ad_fmclidar1_ebz/zc706: Enable CAPTURE_TILL_FULL
  ad_fmclidar1_ebz/zc706: Reduce FIFO size to 2kB
  ad_fmclidar1_ebz: Laser driver runs on ADC's core clock
  ad_fmclidar1_ebz_bd: Delete the FIFO instance

     Because the DMA transfers are going to be relatively small (< 2kbyte),
     the DMA can handle the data rate, even when the frequency of the laser
     driver pulse is set to its maximum value. (200 kHz)

     The synchronization will be done by connecting the generated pulse to
     the DMA's SYNC input. Although, to support 2 or 1 channel scenarios, we
     need to use the util_axis_syncgen module to make sure that the DMA
     catches the pulse, in cases when the pulse width is too narrow. (SYNC is
     captures when valid and ready is asserted)

     Also we have to reset the cpack IP before each pulse, to keep the DMA buffer's
     relative starting point in time fixed, when only 2 or 1 channel is
     active.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 9422da7908 util_axis_syncgen: Initial commit
The module can receive a synchronous or asynchronous pulse with an arbitrary
width and generate a SYNC signal for the DMA Source AXI Streaming interface.

This way we can synchronize the DMA transfers to an external
pulse/signal.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 75d1379618 axi_laser_driver: Initial commit
The laser driver contains the axi_pulse_gen's IP and an additional
register map which controls/monitor the laser driver enable control line
and the over temperature warning line (OTW).

It also contains an interrupt logic, which allows to generate an
interrupt in function of the generated pulse or incoming OTW signal.

The IPs register maps looks as follow:

0x00 - axi_pulse_gen register map
0x80 - axi_laser_driver register map
  0x80 - DRIVER_ENABLE
  0x84 - DRIVER_OTW
  0x88 - EXT_CLK_COUNTER
  0xA0 - IRQ_MASK
  0xA4 - IRQ_SOURCE
  0xA8 - IRQ_PENDING
  0xAC - SEQUENCER_CONTROL
         0 - SEQUENCER_ENABLE
         1 - AUTO_SEQUENCER_ENABLED
  0xB0 - SEQUENCER_SYNC_OFFSET
  0xB4 - AUTO_SEQUENCE
         [ 1: 0] - CHANNEL_SEL_0
         [ 5: 4] - CHANNEL_SEL_1
         [ 9: 8] - CHANNEL_SEL_2
         [13:12] - CHANNEL_SEL_3
  0xB8 - MANUAL_SEQUENCE
         [ 1: 0] - MANUAL_CHANNEL_SEL

Current interrupt sources scheme is:
    - bit 0 : pulse (triggered by the level of the pulse)
    - bit 1 : OTW_N enter (triggered by positive edge of the OTW_N)
    - bit 2 : OTW_N exit (triggered by the level of the pulse)

Generate a reset signal before the pulse which can be used to reset
various IP's of the data path (eg. pack/cpack). This can help to clear out the
internal buffers and registers of these IP, starting clean at the moment when
the actual pulse arrives.

The sequencer has an auto and a manual mode, and can be set to custom
sequences of the TIA channel selection lines sate.

The sequencer in auto mode is synchronized to the pulse, it will change
its state before a generated pulse which will drive the lasers. The
offset between the sequencer beat and the laser driver pulse can be
modified through an AXI register.
2019-08-08 14:26:07 +03:00
Istvan Csomortani d4200aee9a axi_pulse_gen_regmap: Rename the clk output to clk_out 2019-08-08 14:26:07 +03:00
Istvan Csomortani f1403aa593 axi_pulse_gen: Update constraint file
- add missing false paths
 - change the bus skew constraint to a false path, for some reason the
   tool does not change the path's requirement after a set_bus_skew
   constraint
2019-08-08 14:26:07 +03:00
Istvan Csomortani 3a7d0698a8 axi_pulse_gen: Registers should be placed at front of the register space
Because this register map will be integrated into other IPs too, make
sure that the registers are places in the absolute front of the register
space.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 723f5cddfc util_pulse_gen: Expose the internal counter
Expose the internal counter so we can synchronize external signals to,
or relative to, the generated pulse.
2019-08-08 14:26:07 +03:00
Istvan Csomortani 544e2b8ad0 util_pulse_gen: Pulse should not be generated if module is in reset 2019-08-08 14:26:07 +03:00
Istvan Csomortani 75e4c844ba util_pulse_gen: Optimise design in order to improve timing 2019-08-08 14:26:07 +03:00
Arpadi 0680e44330 system_id: deployed ip 2019-08-06 16:53:11 +03:00
Sergiu Arpadi 4fe5f007cb system_id: added axi_sysid ip core and tcl 2019-08-06 16:53:11 +03:00
Arpadi ab3d43be71 up_axi.v: fixed bus width definition
fixed axi_dma_regmap.v bus width missmatch
2019-08-06 13:45:54 +03:00