Commit Graph

146 Commits (fa998a406b7ba75e3d763813635bba423ba7ff50)

Author SHA1 Message Date
Rejeesh Kutty fa998a406b dma: parameter fix 2014-04-24 15:50:16 -04:00
Rejeesh Kutty 314ec3d343 altera-9250/dma: make id width generic 2014-04-24 14:54:19 -04:00
Rejeesh Kutty dfc2bba335 ad9671: updates to allow default adc setup routines 2014-04-23 16:39:28 -04:00
Rejeesh Kutty a1bcf345c6 ad9671: fix spi connections 2014-04-21 13:46:44 -04:00
Adrian Costina 213e852e11 motor_control: Initial commit 2014-04-18 18:57:18 +03:00
Rejeesh Kutty 503096de18 gt: change userready on drp clock 2014-04-17 16:09:55 -04:00
Istvan Csomortani b185d46573 Add a link to EngineerZone
Some users find these projects through github, and they do not know how/where to ask support.
2014-04-15 10:25:18 +03:00
Adrian Costina ba44ee63be fmcomms1: modified the fmcomms1_bd.tcl to make it compatible with latest wfifo 2014-04-14 17:04:04 +03:00
Istvan Csomortani 179d6d601c adi_board.tcl : Use 'global' instead of '$::' 2014-04-14 11:45:35 +03:00
Rejeesh Kutty 38126c404c usdrx1: spi signal definitions 2014-04-11 14:28:23 -04:00
Rejeesh Kutty 06b28d2e24 ad9671: compile fixes 2014-04-11 14:28:22 -04:00
Rejeesh Kutty e92e6b2fd5 ad9671_fmc: changed for ad9671-fmc 2014-04-11 14:28:21 -04:00
Rejeesh Kutty 72e318a247 ad9671_fmc: initial checkin 2014-04-11 14:28:20 -04:00
ATofan 570ec26798 FMCOMMS2: Added sync option 2014-04-11 18:14:48 +03:00
ATofan 99ef34936f Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-04-11 18:14:08 +03:00
U-ANALOG\ACostina c73390b6c9 axi_ad9361: Intermediary check in for altera porting
This is work in progress. It will not work as it is
2014-04-11 17:40:34 +03:00
Adrian Costina d0f04fd788 fmcomms1: Commit AC701 and VC707 projects 2014-04-11 17:35:25 +03:00
Istvan Csomortani c718169f27 adi_board.tcl : Fix the address assignment command
A lot of cores have more than one address segments, therefor need
	to filter out the segment of the axi lite interface
2014-04-11 16:14:56 +03:00
Istvan Csomortani cf5b9b51fd adi_board.tcl : Fix spi ports and hp clocks 2014-04-11 15:31:12 +03:00
Rejeesh Kutty af07f8874f wfifo/rfifo: asynchronous interface 2014-04-10 14:01:40 -04:00
Istvan Csomortani 37e2059fd0 adi_board.tcl : General update
- Split the adi_dma_interconnect to two procedure:
	  adi_dma_interconnect and adi_hp_assign
	- Fix the adi_spi_core
	- Fix the adi_interconnect_lite
2014-04-10 18:29:14 +03:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Rejeesh Kutty 6f36f74eea usdrx1: common board files 2014-04-10 11:05:11 -04:00
Rejeesh Kutty ac1c145a61 usdrx1: initial checkin 2014-04-10 11:05:10 -04:00
Lars-Peter Clausen dc7b3e085c axi_dmac: Fix issues with non 64-bit AXI masters
Make sure that the address generator behaves correctly when the buswidth is not
64-bit. Also since the source and destination can have different widths add
separate parameters for source and destination address alignment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:54:22 +02:00
Lars-Peter Clausen 36ef882da0 axi_dmac: data_mover: Improve timing
We do not know which 'last' condition to use before hand, but we can pre-compute
the result for both conditions and then use them. This removes the comparison
from the already pretty long combinatorial path.

Also simplify a few expressions.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 14:06:44 +02:00
Lars-Peter Clausen 090d3aee04 axi_dmac: Change C_DMA_LENGTH_WIDTH default to 24
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen cb630e36a9 axi_dmac: src_fifo_inf: Simplify data path
Improves timing a bit

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen f9ca4fb8be axi_fifo: Slightly improve timing
It is OK to overwrite invalid data with other invalid data.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 4c9647f289 axi_dmac: axi_register_slice: Provide default values for registers
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen fa5ba6c09d axi_dmac: Make cyclic mode runtime configurable
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 7ca43f4920 axi_dmac: address_generator: Make 'len' registered
Slightly improves the timing.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 66e6c1cc21 axi_dmac: axi_register_slice: Remove reset "latch" from datapath
Move the datapath updates out of the else branch of the reset condition.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
Lars-Peter Clausen 799d2384d8 up_xfer_cntrl: Remove extra semicolon
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-04-10 13:50:39 +02:00
ATofan 9d19145713 Merge branch 'master' of https://github.com/analogdevicesinc/hdl 2014-04-10 10:50:53 +03:00
ATofan 5aac9d7288 FMCOMMS2 added sync option
Added signals to allow synchronisation of multiple AD9361.
2014-04-10 10:46:42 +03:00
Rejeesh Kutty fbfd658f0d zc706: added pl ddr3 mig 2014-04-09 15:58:12 -04:00
Istvan Csomortani e73952a694 ad9467 : initial checkin 2014-04-09 17:34:40 +03:00
Rejeesh Kutty 8bebc5e3d4 ad9671: initial checkin 2014-04-07 13:01:10 -04:00
Istvan Csomortani 5b0e37b97a adi_project.tcl : Modify implementation strategy
- Change implementation strategy to Performance Explore.
	  At some projects, this could prevent timing issues, it not
	  increase the overall implementation time in a dramatic way.
2014-04-07 15:02:38 +03:00
rejeesh kutty 4116247fc0 Update README.md 2014-04-04 16:30:28 -04:00
Rejeesh Kutty 33979fc533 fixes to improve timing - fifo for clock domain transfers 2014-04-04 13:49:53 -04:00
Rejeesh Kutty 6a19b34a00 a5gt: added tightly coupled memory 2014-04-03 20:50:17 -04:00
Rejeesh Kutty 04ab34c8ed a5gt: ethernet assignments 2014-04-03 20:50:16 -04:00
Rejeesh Kutty 12e5cc91bd make signaltap/timing part of the flow 2014-04-03 20:50:15 -04:00
Adrian Costina d0a8b4a63c kc705,common: Mem_interconnect maximize performance
For FMCOMMS1, when both the ADC and DAC DMAs are active, the system was
unstable. With this fix, it the system seems to be stable.
2014-04-03 15:59:33 +03:00
Rejeesh Kutty f8f2684b7e up_gt: eyescan delay bug fix 2014-04-02 16:45:41 -04:00
Rejeesh Kutty e85153b5dd altera hal version 2014-04-01 21:12:11 -04:00
Rejeesh Kutty 80e5051894 axi_jesd_gt: initial checkin 2014-04-01 15:14:28 -04:00
Rejeesh Kutty 2472d61daf ad_gt_es: status asserted early for latency 2014-04-01 15:06:51 -04:00