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5167 Commits (fa610d36c6c401773f015696bc0b86f41d7a2018)

Author SHA1 Message Date
Istvan Csomortani fa610d36c6 ad_ghdl_dir: Fix global variable name 
In #PR318 the global variable $ad_phdl_dir name were changed to
$ad_ghdl_dir.
 2019-07-23 10:29:37 +01:00
Adrian Costina 6655829bc7 daq2: VC707: Remove project 2019-07-22 13:25:46 +01:00
Adrian Costina a6cff0f804 motcon2_fmc: Remove project 2019-07-22 13:23:43 +01:00
Istvan Csomortani 6a721c0bf0 adi_env: Update system level environment variable definition 
Our internal repository was changed from phdl to ghdl. Update the
adi_env.tcl scripts and other scripts, which depends on the $ad_ghdl_dir
variable. This way the tools will see all the internal IPs too.
 2019-07-22 11:00:45 +03:00
AndreiGrozav ce5aadb3e4 adrv9361z7035/common/ccbox_constr.xdc: Cosmetics only 2019-07-17 10:37:30 +03:00
AndreiGrozav 6f627c2105 adrv9361z7035/ccbox: Keep by default in powerdown the 12V PS 
Because of build hazards, the power supply can be randomly powered on,
when the pin is left in high impedance.
 2019-07-17 10:37:30 +03:00
Istvan Csomortani 3031ec3bdd adi_jesd204: Move some leftover files to intel directory 
These file were left in the old library directory, move them to the new
library/intel directory.
 2019-07-10 10:57:12 +01:00
AndreiGrozav 5f1cb18c9b ad7616_sdz/zc706: Fix Build 
- Fix typo
- Remove the unused(old flow) ps interupts
 2019-07-10 12:51:42 +03:00
Laszlo Nagy 1f1b2b4fa3 axi_dmac:axi_dmac_ip: Fix AXI Stream signals bundle 
The unused AXI stream signals have to be added to the AXIS interface so
they don't hang loose on the IP in the block design.
 2019-07-08 16:08:06 +03:00
Istvan Csomortani bb8912b766 axi_hdmi_tx: Update parameter name 2019-06-29 06:53:51 +03:00
Istvan Csomortani 165c8a943b gitignore: Update to the new naming convention 2019-06-29 06:53:51 +03:00
Istvan Csomortani e1d9a36ae0 scripts/adi_project_intel: Rename ALT_NIOS_MMU_ENABLED to NIOS_MMU_ENABLED 2019-06-29 06:53:51 +03:00
Istvan Csomortani 76620bc890 avl_adxcvr: Rename variables with alt_* pre-fix 
- alt_sys_clk -> sys_clk
  - alt_xcvr_rst -> xcvr_rst
  - alt_ref_clk -> ref_clk
  - alt_fpll_rst_cntrol -> fpll_rst_control
  - alt_core_pll -> core_pll
  - alt_core_clk -> core_clk
  - alt_rst_cntrol -> rst_control
  - alt_lane_pll -> lane_pll
  - alt_ip -> jesd204_ip
  - alt_xphy -> avl_xphy
  - alt_phy_* -> phy_*
 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6a42f54b1e axi_ad9361/intel: Rename varibles with alt_* pre-fix 2019-06-29 06:53:51 +03:00
Istvan Csomortani 0f7a3b953a scripts/adi_ip_intel: Rename the ad_alt_intf to ad_interface 2019-06-29 06:53:51 +03:00
Istvan Csomortani 04ce10a570 cosmetics: Change Altera to Intel in comments 2019-06-29 06:53:51 +03:00
Istvan Csomortani 2f0dbe6151 intel_mem_asym: Rename the alt_mem_asym to intel_mem_asym 2019-06-29 06:53:51 +03:00
Istvan Csomortani 1e074726db intel_serde: Rename alt_serdes to intel_serdes 2019-06-29 06:53:51 +03:00
Istvan Csomortani b0fbe1bb57 util_clkdiv: Seperate the IP source into an intel and xilinx version 2019-06-29 06:53:51 +03:00
Istvan Csomortani 84bd50d437 alt_ifconv: Remove unused IP 2019-06-29 06:53:51 +03:00
Istvan Csomortani d5e5fcf17a alt_mul: Remove unused IP 2019-06-29 06:53:51 +03:00
Istvan Csomortani 5329458a62 library/scripts: Rename adi_ip_alt.tcl to adi_ip_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 363494ab9c library/scripts: Rename adi_ip.tcl to adi_ip_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 6e6f1347d7 project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani ec67a381e4 adi_project: Rename the process adi_project_altera to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani 79b6ba29ce all: Rename altera to intel 2019-06-29 06:53:51 +03:00
Istvan Csomortani d79fa179a3 spi_engine: Fix sync_bit instances 2019-06-28 11:18:29 +03:00
Sergiu Arpadi ba4a915af0 ad40xx/zed: fixed system_bd 
spi_engine_execution: fixed sdo default
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 42b14f341a axi_spi_engine: Generate false paths only on ASYNC_CLK mode 2019-06-28 11:18:29 +03:00
Istvan Csomortani f4de1fecdc spi_engine_execution: Add an additional register stage for the physical SPI 
The main reason is to improve timing when the SPI clock is more than
50 MHz. (the SPI Engine's spi_clk is more than 100MHz)
 2019-06-28 11:18:29 +03:00
Istvan Csomortani cf9d0814d5 ad40xx/zed: Place all the SPI registers near IOB 2019-06-28 11:18:29 +03:00
Istvan Csomortani 77ffa1f8ac util_dec256sinc24b: Fix the accumulator 
Do a similar fix as for the decimation stage. (ab2788)
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 10e1abc22f ad40xx_fmc/zed: Delete IOB TRUE constraints 
Vivado can not apply the IOB TRUE constraint to only one bit of a
registers. So these constraints will generate several CRITICAL WARNING.

Taking into consideration the maximum used frequencies and current
architecture these constraints are not critical.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 158b018f58 spi_execution: Improve timing by defining resets for the shift registers 2019-06-28 11:18:29 +03:00
Istvan Csomortani d802ece39e spi_engine: Reindent execution module source code 2019-06-28 11:18:29 +03:00
Laszlo Nagy 6b110b6fb8 ad5758_sdz/zed: system constraint file cleanup 
removed redundant PACKAGE_PIN properties
 2019-06-28 11:18:29 +03:00
Laszlo Nagy 0f2a1e7602 ad5758_sdz: Initial commit 
Initial version of AD5758 SDZ evaluation board support on ZedBoard.
No critical warnings in the Vivado log.
Bitstream generation passing.
Bring-up on actual board not done.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 9ab88f1200 ad40xx: Initial commit 2019-06-28 11:18:29 +03:00
Istvan Csomortani 94f8d1b424 util_axis_upscale: Sign extension must be done separately for each channel 2019-06-28 11:18:29 +03:00
Istvan Csomortani 5f8269da03 spi_egine: Add a new register for dynamic transfer length configuration 2019-06-28 11:18:29 +03:00
Istvan Csomortani 40fbb37d6f spi_engine: Add additional synchronization FIFO's to axi_spi_engine 
Add additional synchronization FIFOs to several interfaces of the
axi_spi_engine module, to prevent metastability and timing issues in
case when the system clock and the SPI clock are asynchronous.
 2019-06-28 11:18:29 +03:00
Istvan Csomortani 91801bfe0d spi_engine: Update the ad_rst instance 2019-06-28 11:18:29 +03:00
Istvan Csomortani 68c1f92066 spi_engine: Add a CDC fifo for the SYNC interface too 2019-06-28 11:18:29 +03:00
Istvan Csomortani a19f6197cc spi_engine: Fix indentation of axi_spi_engine.v 2019-06-28 11:18:29 +03:00
Istvan Csomortani b81c8373e5 spi_engine: In read only mode SDO line should stay in its default level 2019-06-28 11:18:29 +03:00
Istvan Csomortani 85bbf95c57 spi_engine/offload: SDI_READY should be asserted while offload is inactive 2019-06-28 11:18:29 +03:00
Istvan Csomortani 746f457ef9 spi_engine: Software reset should reset the offload control registers too 2019-06-28 11:18:29 +03:00
Istvan Csomortani 19655b8092 spi_engine: Define SDO default state 
There are devices where the SDO default state, between transactions, is
not GND, rather VCC.

Define a parameter, which can be used to set the default state of the
SDO line.
 2019-06-28 11:18:29 +03:00