Commit Graph

26 Commits (f9ffaf457d34b418a2429077d5ef98316cf31c07)

Author SHA1 Message Date
Adrian Costina 1ef83bd88b axi_ad9671: Updated port names. Fixed synchronization of the rx_sof with the ad_jesd_align module, so that data valid is assigned correctly 2015-05-23 00:16:27 +03:00
Rejeesh Kutty af7afd7366 ad9671: delay changes 2015-05-19 12:53:56 -04:00
Adrian Costina a61a195e3f Makefiles: Updated makefiles to add the new constraints as dependecies 2015-04-23 11:16:39 +03:00
Adrian Costina f1f8c14813 axi_ad9671: Added CDC and reset constraints 2015-04-23 10:39:11 +03:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina 374f82e7de makefiles: The clean command for library won't remove the xml files, except for component.xml.
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Adrian Costina f79a152958 Makefiles: updated all makefiles adding clean functionality 2015-04-03 11:57:54 +03:00
Rejeesh Kutty 500f71af2f makefile: added 2015-04-01 16:27:46 -04:00
Adrian Costina fbce64411e axi_ad9671: added synchronization interface to altera core 2014-10-29 18:20:26 +02:00
Adrian Costina fe92b8b210 axi_ad9671: Updated synchronization mechanism to have a software defined starting code 2014-10-22 13:10:28 +03:00
Adrian Costina 8934a66013 usdrx1: Update project so that the AD9671 cores can be synchronized 2014-10-13 17:06:40 +03:00
Rejeesh Kutty 4bdb3cd262 axi_ad9671: altera axi4lite changes 2014-10-09 15:25:07 -04:00
Rejeesh Kutty 6125bbecc3 axi_ad9671: altera axi4lite changes 2014-10-09 15:25:06 -04:00
Adrian Costina 2dfcb0c599 usdrx1: Initial commit for a5gt
axi_ad9671: added start of frame information to the altera core.
2014-10-07 19:41:54 +03:00
Rejeesh Kutty de33722470 up/constr: independent read/write and local constraints 2014-10-02 14:35:59 -04:00
acostina 5af2474d51 usdrx1: axi_ad9671 / axi_jesd_gt added signal for frame synchronization 2014-09-23 22:44:33 -04:00
Lars-Peter Clausen 41cc92ef49 Remove BASEADDR/HIGHADDR parameters
This is unused and unneeded. The AXI interconnect will make sure that a
peripheral only gets requests that are meant for it, there is no need to
check the address in the peripheral itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2014-09-11 12:26:37 +02:00
Lars-Peter Clausen 50faf0c53a Remove executable flags from non-exectuable files 2014-09-09 15:05:06 +02:00
Rejeesh Kutty da913864c9 ad9671_fmc: updates to match recent core changes 2014-08-28 13:16:52 -04:00
Rejeesh Kutty 08a12aaf23 library: register map updates on 9467, 9643 and 9671 2014-07-31 15:19:45 -04:00
Rejeesh Kutty f55288ef5d ad9671: altera - base changes 2014-04-28 21:31:18 -04:00
Rejeesh Kutty 02e8b27626 initial checkin-9250 copy 2014-04-28 21:31:16 -04:00
Rejeesh Kutty dfc2bba335 ad9671: updates to allow default adc setup routines 2014-04-23 16:39:28 -04:00
Rejeesh Kutty 96541f0a7f usdrx1: zc706 updated for usdrx1 2014-04-10 11:05:13 -04:00
Rejeesh Kutty 8bebc5e3d4 ad9671: initial checkin 2014-04-07 13:01:10 -04:00