02ada3bbf7
a10gx: Delete input/output delay definitions
...
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
ee01ea3736
daq2/a10gx: Add cfi_flash to qsys
...
+ Add cfi_flash to qsys
+ Set nios reset vector to cfi_flash
2017-10-04 11:30:29 +01:00
17d3e3c64b
daq2: daq2_qsys.tcl: Convert to ADI JESD204
...
Convert the DAQ2 project for Intel/Altera platforms to the ADI JESD204
framework.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2017-08-21 11:21:42 +02:00
3f92381bd0
daq2/a10gx- project/constraint updates
2017-06-06 16:09:15 -04:00
c4b4bdc415
daq2/a10gx- constraints remove 16.0
2017-05-16 10:09:42 -04:00
cfcb269d38
a10gx- change ddr to 1G
2017-05-15 09:32:36 -04:00
5df30ac6b0
daq2/a10gx- xcvr sharing
2016-09-12 14:57:50 -04:00
ae1dd1d58e
daq2/a10gx- qsys updates
2016-06-07 12:28:04 -04:00
7a4a7edfba
daq2/a10gx: 10AX115S3F45E2SGE3 version
2016-04-20 16:07:41 -04:00
ad9ecbbbb6
daq2: Updated a10gx project to quartus 15.1.1
2016-02-05 17:43:05 +02:00
15be942b74
daq2-a10gx- ignore cpu2ddr-io paths
2015-08-27 13:54:05 -04:00
78cf0fce0e
ddr/eth- pll refclock is defined by the cores
2015-08-21 14:42:15 -04:00
b3102b5095
daq2/a10gx-- xcvr+base changes
2015-07-21 11:01:45 -04:00
97b8468819
daq2- constraints
2015-07-20 09:32:17 -04:00
a2e7fb9491
daq2/a10gx: qsys signal tap version
2015-07-13 10:07:18 -04:00
075b1e5424
daq2/a10gx: added axi_jesd_xcvr control
2015-07-07 10:22:36 -04:00
d6b1260678
daq2/a10gx- signal tap + gpio
2015-06-19 14:32:58 -04:00
4a701d3895
a10gx- no-ddr
2015-06-01 11:00:02 -04:00
75e055dab9
daq2/a10gx- initial commit
2015-05-11 11:56:23 -04:00
Istvan Csomortani
STEVE KRAVATSKY
Lars-Peter Clausen
Rejeesh Kutty
Adrian Costina