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13 Commits (f957d81db17d85f1bc6e09317cb7cac135388782)

Author SHA1 Message Date
stefan.raus 6c0a07c24b cn0506_mii/rgmii on a10soc: update to Quartus 21.2 
Remove contraints related to quartus version so that
cn0506_mii and cn0506_rgmii on arria10 to be built
with default quartus version.

Signed-off-by: stefan.raus <stefan.raus@analog.com>
 2022-03-31 09:55:56 +03:00
Adrian Costina 62dc310794 Revert "intel: Update projects to use ad_iobuf instead of ALT_IOBUF" 
This reverts commit a3a610728c.

Quartus doesn't instantiate correctly the buffer
 2022-02-09 17:39:29 +02:00
LIacob106 38c489d254 projects: set Quartus version for cyclone5, cn0506_mii and cn0506_rgmii 2021-12-15 17:13:38 +02:00
Adrian Costina 591a23156b Makefiles: Update header with the appropriate license 2021-09-16 16:50:53 +03:00
Sergiu Arpadi 6f2f2b8626 makefile: Regenerate make files 2021-01-20 01:02:56 +02:00
sergiu arpadi acbbd4636a sysid: Upgrade framework, header/ip are now at 2/1.1.a 
Unify tcl scripts; rename adi_pd_intel.tcl to adi_pd.tcl
add git branch to internal use area; update log prints;
update xilixn projects; fix cn0506 sysid script;
 2021-01-20 01:02:56 +02:00
Adrian Costina a3a610728c intel: Update projects to use ad_iobuf instead of ALT_IOBUF 2020-11-02 16:13:35 +02:00
Istvan Csomortani 37254358dd makefile: Regenerate make files 2020-10-20 12:51:10 +03:00
Sergiu Arpadi d8ab27b2af sysid: Remove cstring init string 2020-09-30 19:12:24 +03:00
Sergiu Arpadi 3241924d14 sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
StancaPop 05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl 
Rename projects for consistency
 2020-02-06 16:32:40 +02:00
AndreiGrozav e00ee136f6 cn0506_mii Updates for Rev B board 
Because of the rmii mode requirements(external 50MHz clock) the
board will have the rx_err signal replaced on the FMC connector with the
50MHz external clock (D08/D20).
The rx_er will be shifted to the D9/D21 pins.
 2020-02-03 11:20:18 +02:00
AndreiGrozav 4941d89fff cn0506_mii: Add support on a10soc 2019-10-18 19:09:04 +03:00