Commit Graph

572 Commits (f91fbf1bc18426ff3e81cc8561ec5c008b1d38ca)

Author SHA1 Message Date
Rejeesh Kutty 32f7e98afd ad9361: add ddr-edgesel 2015-05-06 16:58:47 -04:00
Adrian Costina 670850183b axi_hdmi_tx: Updated constraints as in fmcomms2/zc702 project they were not correctly applied 2015-05-06 18:53:19 +03:00
Istvan Csomortani a7c96fdac8 util_dacfifo: General clean up of the IO, input/output data has the same width 2015-05-06 16:32:44 +03:00
Istvan Csomortani 0613dca0b7 axi_dmac: Move the 'axis_xlast' logic into the dest_axi_stream module 2015-05-06 16:10:28 +03:00
Adrian Costina 949abcdc8f Makefile: Updated makefiles so that the project recipe does not depend on lib 2015-05-06 14:58:29 +03:00
Istvan Csomortani 65af205d6b axi_dmac: Add axis_last control signal to the Master AXI Streaming interface
This control signal can be overwritten by the up_axis_xlast/up_axis_xlast_en bits, in order to create a single stream, which is contains multiple streams.
This can be use to fill up the DACFIFO module.
2015-05-06 13:54:31 +03:00
Adrian Costina 233cc111d2 util_pmod_adc: Used generated clock for the ADC SPI. Works by default at 6.25MHz 2015-05-05 23:33:13 +03:00
Adrian Costina 3517b6941c adv7511:kcu105, axi_hdmi_tx, axi_spdif_tx constraints modified so they apply to ultrascale 2015-05-05 10:06:26 +03:00
Rejeesh Kutty 707b285669 prcfg: bb def 2015-05-04 10:24:13 -04:00
Adrian Costina be32715ab3 axi_adcfifo: Updated constraints 2015-04-30 14:23:24 +03:00
Adrian Costina d623f77453 axi_jesd_gt: Added rx_jesd_rst and tx_jesd_rst.
Resets for both up clock domain and rx clock domain are needed in some projects
2015-04-30 12:07:36 +03:00
Adrian Costina 463c4d4d28 util_wfifo: Added constraint for the resetn path 2015-04-30 12:05:02 +03:00
Adrian Costina 392ba31a07 axi_hdmi_rx: Updated constraints 2015-04-30 12:04:15 +03:00
Adrian Costina 288b9cccff Makefile: Added makefiles for imageon_loopback project. Updated axi_ad9152, util_gmii_to_rgmii, util_wfifo to include constraints file 2015-04-28 15:22:37 +03:00
Adrian Costina a7a2d194e9 axi_jesd_gt: Switched rx_rst and rx_rst_done to up clock domain, to be compatible with xilinx JESD core 2015-04-28 15:04:18 +03:00
Adrian Costina c36186f75a axi_ad9643: Added adc_rst output 2015-04-28 14:52:24 +03:00
Adrian Costina 8ee3f64a65 axi_ad9265: Added adc_rst output 2015-04-28 14:51:14 +03:00
Adrian Costina 67c581cef8 util_wfifo: Updated to be used with adc_rst from the adc_clk clock domain 2015-04-28 14:50:00 +03:00
Adrian Costina 1ad87aa27c util_wfifo: Added constraints 2015-04-27 11:19:56 +03:00
Adrian Costina 81d4e1d9b1 axi_clkgen: Updated constraints 2015-04-27 11:19:15 +03:00
Adrian Costina d950f5ffcd axi_ad9122: Updated constraints 2015-04-27 11:18:52 +03:00
Istvan Csomortani 9fba4cb2ef util_dacfifo: Add support for Slave AXI stream interface.
The FIFO can be initialized through an AXI stream interface too.
2015-04-27 10:40:55 +03:00
Lars-Peter Clausen 3a02998e9a axi_ad9152/axi_ad9152_ip.tcl: Fix typo
axi_ad9152_constr.v -> axi_ad9152_constr.xdc

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-24 09:41:43 +02:00
Adrian Costina a9924e6401 util_gmii_to_rgmii: Added constraints 2015-04-23 16:53:57 +03:00
Adrian Costina bd06bae8c2 library: Modified the adi_ip.tcl script
The constraints processing order changed to "late" instead of "early", in order for all the clocks in the system to be already created when the IP constraints are applied
2015-04-23 14:31:23 +03:00
Adrian Costina a61a195e3f Makefiles: Updated makefiles to add the new constraints as dependecies 2015-04-23 11:16:39 +03:00
Adrian Costina d42c0bc431 axi_jesd_gt : Added CDC and reset constraints 2015-04-23 11:03:51 +03:00
Adrian Costina 1b4e6bdc80 axi_mc_speed : Added CDC and reset constraints 2015-04-23 10:50:49 +03:00
Adrian Costina 6d28d217f1 axi_mc_current_monitor: Added CDC and reset constraints 2015-04-23 10:49:43 +03:00
Adrian Costina d0b2d531bc axi_mc_constroller: Added CDC and reset constraints 2015-04-23 10:47:35 +03:00
Adrian Costina d0571a912f axi_hdmi_tx: Added CDC and reset constraints 2015-04-23 10:46:04 +03:00
Adrian Costina cc7d9f9d54 axi_clkgen: Added CDC and reset constraints 2015-04-23 10:44:37 +03:00
Adrian Costina d1558df625 axi_ad9739a: Added CDC and reset constraints 2015-04-23 10:42:27 +03:00
Adrian Costina 97dc7ea004 axi_ad9680: Added CDC and reset constraints 2015-04-23 10:40:41 +03:00
Adrian Costina f1f8c14813 axi_ad9671: Added CDC and reset constraints 2015-04-23 10:39:11 +03:00
Adrian Costina 744a15a0ba axi_ad9652: Added CDC and reset constraints 2015-04-23 10:37:15 +03:00
Adrian Costina eca616a3ae axi_ad9643: Added CDC and reset constraints 2015-04-23 10:35:12 +03:00
Adrian Costina a62415b0ab axi_ad9625: Added CDC and reset constraints 2015-04-23 10:33:51 +03:00
Adrian Costina b4a09daf89 axi_ad9467: Added CDC and reset constraints 2015-04-23 10:30:33 +03:00
Adrian Costina ac79c65b81 axi_ad9434: Added CDC and reset constraints 2015-04-23 10:28:46 +03:00
Adrian Costina a6cb6b7672 axi_ad9265: Added CDC and reset constraints 2015-04-23 10:27:29 +03:00
Adrian Costina 08f19d489f axi_ad9250: Added CDC and reset constraints 2015-04-23 10:25:19 +03:00
Adrian Costina 734fdab326 axi_ad9234: Added CDC and reset constraints 2015-04-23 10:23:22 +03:00
Adrian Costina 09f05cf8e9 axi_ad9152: Added CDC and reset constraints 2015-04-23 10:21:52 +03:00
Adrian Costina 3526145992 axi_ad9144: Added CDC and reset constraints 2015-04-23 10:19:43 +03:00
Adrian Costina e7ce2b200d axi_ad9122: Added CDC and reset constraints 2015-04-23 10:17:53 +03:00
Adrian Costina 691c54e0dd axi_ad6676: Added CDC and reset constraints 2015-04-23 10:16:29 +03:00
Lars-Peter Clausen 7b073aaec1 axi_dmac: Always generate local interrupt for asynchronous interfaces
While the reset for the memory mapped AXI master is synchronous to some
clock it is not necessarily synchronous to the clock used for that
interface. So always generate a local reset signal to avoid problems that
could result from this.

While we are at it also update the code to only generate a local reset if
the interface is asynchronous to the register map, otherwise use the
register map reset.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
Lars-Peter Clausen 5edcc753ec axi_dmac: Ignore timing on more debug signals
Ignore the timing path from the current DMA address to the register map,
this is just a debug signal at the moment.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-22 13:22:23 +02:00
Lars-Peter Clausen ae808ba942 axi_dmac: Fix block ram constraint
If the internal FIFO is larger than one block ram there will be multiple
BRAMs called ram_reg[0], ram_reg[1]. Modify the BRAM constraint rule so that
it matches these as well.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 19:56:42 +02:00
Istvan Csomortani a100ecd308 util_dacfifo: Update BRAM DAC Fifo
The fifo will be placed between the DMAC and the Upack module, all the interfaces were updated.
2015-04-21 15:45:56 +03:00
Lars-Peter Clausen 988bf60747 axi_ad9361: Add ASYNC_REG properties to CDC regs and add missing -datapath_only
Set the ASYNC_REG property on the bit synchronizer CDC control regs. This
hint to Vivado that the registers are used for CDC purposes.

Also use -datapath_only for the set_max_delay constraints on the CDC data
path to remove the hold time requirement.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-21 10:15:02 +02:00
Lars-Peter Clausen 996d0fe8a4 axi_hdmi_tx: Only mark HDMI clocks asynchronous to each other
Currently the axi_hdmi_tx core constraints marks all its clocks asynchronous
to all other clocks in the system. This is a bit unfortunate as these
constraints are not restricted to the axi_hdmi_tx, but affect all cores in
the system, some of which might actually have timing constraints on CDC
paths.

The proper way to fix this is to add constraints for the axi_hdmi_tx core
CDC paths. For now only mark the interface clock asynchronous to the HDMI
clock, as this is easy to do and an improvement over the current situation,
as other cores are no longer affected.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:18:51 +02:00
Lars-Peter Clausen e3b834ea02 axi_ad9361: Add CDC constraints
Add proper constraints for all the CDC synchronizer paths to the axi_ad9361
core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 20:12:06 +02:00
Lars-Peter Clausen 0dc3bb8905 axi_dmac: Fix src_reponse_fifo control signals
The src_response_fifo has been removed from the design, but we still need to
assert the ready and empty control signals for things to work properly.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 19:51:37 +02:00
Lars-Peter Clausen 42a9da0659 axi_dmac: Only apply CDC constraints if clocks are asynchronous
We really only want to apply the CDC constraints if the clocks are actually
asynchronous. Unfortunately we can't use if ... inside a xdc script. But we
can use expr which has support for a ? b : c if-like expression. We can use
that to create helper variables that contains valid clock when the clock
domains are asynchronous or {} if they are not. Passing {} as
set_false_path/set_max_delay as either the source or destination will cause
it to abort and no constraints will be added.

Also add -quiet parameters to avoid generating warning if the constraints
could not be added.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
Lars-Peter Clausen 9c249d25ab axi_dmac: Make internal resets active high
All the FPGA internal control signals are active high, using a active low
reset inserts a extra invert LUT. By using a active high reset we can avoid
that.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-17 17:20:25 +02:00
Adrian Costina dc2b37bd0c Makefile: Added top level Makefile. Modified behavior of clean and clean-all
Clean ran for a project will clean only the project files.
Clean-all ran for a project will clean also the library files on which the project depends.
The clean commands will only remove specific files and directories.

The top Makefile allows several options(per suggestion from jameyhicks):
make fmcomms1.zed will run "make all" in projects/fmcomms1/zed/
make clean will run "make clean" for all the projects
make clean-all will run "make clean" for all the projects and libraries
make lib will run "make all" for the library files
2015-04-17 17:22:38 +03:00
Adrian Costina fd2f5836f0 axi_dmac: Fixed type in the altera hardware file 2015-04-17 14:59:47 +03:00
Lars-Peter Clausen dfc22fc7de axi_i2s_adi: Overhaul CDC
* Generate a separate synchronous reset for the data clock domain.
* Add missing stage to toggle synchronizers.
* Give a common prefix to CDC elements and add the proper constraints to the
  XDC file
* Remove some unnecessary resets

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
Lars-Peter Clausen 8289262807 axi_spdif_tx: CDC overhaul
Use common prefix for CDC elements and add the proper constraints to the XDC
file. And add a missing stage to the toggle synchronizers.

Also drop a some unnecessary resets.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
Lars-Peter Clausen 9183f2287a axi_spdif_tx: Use adi_ip_constraints
Use adi_ip_constraints to add the constraints file instead of open-coding
it.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
Lars-Peter Clausen bfd84edc46 adi_ip.tcl: adi_ip_constraints: Add support for VHDL projects
Match both xilinx_verilogsynthesis and xilinx_vhdlsynthesis when getting the
file group.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:28 +02:00
Lars-Peter Clausen 7c97e192f2 dma_fifo: Simplify FIFO WE condition
The only time we must not write to the FIFO is when it is full as this will
overwrite the first sample.  Under all other conditions it is ok to write
data. If that data is invalid it will be overwritten when valid arrives.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 17:48:22 +02:00
Adrian Costina 374f82e7de makefiles: The clean command for library won't remove the xml files, except for component.xml.
Updated also the dmac dependencies
2015-04-16 11:53:27 +03:00
Lars-Peter Clausen 34aa0cfda2 Partially revert "axi_dmac: Set proper constraints"
This partially reverts commit f51c941c2d. The
commit accidentally removed the HDMI core constraints.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-16 10:01:19 +02:00
Lars-Peter Clausen f13666cd81 ad9361: axi_dmac_constr: Fix typo 2015-04-16 10:01:19 +02:00
Lars-Peter Clausen f51c941c2d axi_dmac: Set proper constraints
Instead of just marking all clock domains as asynchronous set the
appropriate constraints for each CDC path.

For single-bit synchronizers use set_false_path to not constraint the path
at at all.

For multi-bit synchronizers as used for gray counters use set_max_delay with
the source clock period domain to make sure that the signal skew will not
exceed one clock period. Otherwise one bit might overtake another and the
synchronizer no longer works correctly.

For multi-bit synchronizers implemented with hold registers use
set_max_delay with the target clock period to make sure that the skew does
not get to large, otherwise we might violate setup and hold time.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:26 +02:00
Lars-Peter Clausen b14721b8ae library: Use common prefix for CDC signal names
Use a common naming scheme for CDC signals to make it easier to create
constraints for them.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:22 +02:00
Lars-Peter Clausen c9206433b5 adi_ip.tcl: Allow to specify processing order for adi_ip_constraints
In order to be able to use get_clocks in a constraint file the constraint
file needs to run after the constraint file that creates the clock. Allow to
specify the processing order when adding a constraint file to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:15 +02:00
Lars-Peter Clausen 24df683a2a axi_dmac: Disable src_response_fifo for now
The result of the src_response_fifo is currently not used so disable it for
now.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:12 +02:00
Lars-Peter Clausen 4062aa2860 util_axis_fifo: Fix reset signal
Some of the synchronizers were using the wrong reset signal, fix this.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:11 +02:00
Lars-Peter Clausen 762fa3290b util_axis_fifo: Add room and level outputs
Add a room output on the input side that reports how many free entries the
FIFO has and a level output on the output side that reports how many valid
entries are in the FIFO.

Note that the level output is only accurate if the output of the FIFO is not
registered, otherwise it might be off by one.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:09 +02:00
Lars-Peter Clausen ae4e7a0c37 util_axis_fifo: Add option to disable registered output
Add a option to specify whether the FIFO should have a registered output
stage or not. This is useful if the user wants to implement that stage
itself.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:08 +02:00
Lars-Peter Clausen f6594e276e Bring back AXIS FIFO as a separate module
Bring back the AXIS FIFO as a separate module instead of embedding it into
the DMAC module. This makes it possible to use it in other modules outside
of the DMAC.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:06 +02:00
Lars-Peter Clausen 8fc4b0630e util_axis_resize: Fix typo
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-15 17:20:04 +02:00
Rejeesh Kutty cb98e3e151 adcfifo: unused process 2015-04-13 13:31:50 -04:00
Adrian Costina 95e41e50a6 axi_dmac: Make all clocks asynchronous 2015-04-11 12:04:55 +03:00
Adrian Costina 7d22399860 util_axis_resize: Fixed makefile 2015-04-09 18:06:56 +03:00
Adrian Costina e9bd4b3512 axi_dmac: Updated altera core dependency, changed fifo files location 2015-04-09 17:58:21 +03:00
Adrian Costina 780455d68c Makefile: Updated makefiles. Added makefiles for altera 2015-04-09 17:57:06 +03:00
Istvan Csomortani b7d8e38c94 util_dacfifo: General update
+ Clean out the code, delete unnecessary flops
+ Add support for channel count (C_CH_CNT)
+ FIFO write (data from DMAC/upack) : valid just when xfer_req is asserted, address is free running, new xfer_req resets the address
+ FIFO read (data to DAC) : free running, reads to max address
2015-04-09 11:43:37 +03:00
Lars-Peter Clausen 668b8bda62 util_axis_resize: Add support for specifying the endianness
Add support for specifying whether the lsb of the larger bus are mapped to
the first or the last beat on the smaller bus.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen f1eb1c6064 util_axis_resize: Add support for non power-of-two ratios
Update the axi_repack core so it can handle non power-of-two ratios between
the input and output stream width. The ratio still needs to be a integer
though.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen b6458f9aab axi_dmac: Move axi_repack block to its own module
Move the axi_repack block to its own module. This allows it to use it
outside of the DMA controller.

Also rename it to util_axis_resize to better reflect its function.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:55:17 +02:00
Lars-Peter Clausen 8a47d0f94b adi_ip: Add helper function to add dependency to a IP core
Add a helper function that allows to add dependencies to IP cores to the
current IP core, this makes it possible to use a module from the other IP
without having to add the file itself to the current core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 15:52:41 +02:00
Lars-Peter Clausen 88abf98bd6 adi_env.tcl: Make default ad_hdl_dir path detection more robust
Instead of using a path relative to the current working directory use a path
relative to the location of the adi_env.tcl script.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 14:43:56 +02:00
Lars-Peter Clausen bdaad46704 axi_dmac: Remove up_write signal
up_write is just an alias for up_wreq these days. Just always use the later
and remove the former.
2015-04-08 14:43:56 +02:00
Lars-Peter Clausen 98609527e3 axi_i2s: Add I2S interface definition
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.

Using interface pins also unclutters the connections in the Vivado block
design view a bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 86e6f67d4b util_i2c_mixer: Add I2C interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen fa696adc98 util_dac_unpack: Add fifo_wr interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 978f41cbe8 util_adc_pack: Add fifo_wr interface
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 6ba0667939 axi_dmac: Add fifo_wr/fifo_rd interfaces
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen c82b186610 Add interface definitions for the fifo_rd and fifo_wr interfaces
Using interface definitions makes it possible to group pins of a peripheral
into a interface pins. This allows us to use connect_bd_intf_net to connect
all pins of the interface instead of having to manually call connect_bd_net
for each for the pins.

Using interface pins also unclutters the connections in the Vivado block
design view a bit.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen 11cc18be79 adi_ip.tcl: Initialize ip_repo_paths
Initialize ip_repo_paths so that when building a peripheral we have access to the interface definitions stored in the repository.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Lars-Peter Clausen d17cd22ef1 adi_ip.tcl: Allow to directly specify the vlnv string for adi_add_bus()
Modify the adi_add_bus() function to take the full vlnv strings instead of just the bus type.

This makes the function more flexible and e.g. allows to handle buses from other vendors.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-04-08 13:29:25 +02:00
Rejeesh Kutty 0d0c15df98 axi_adcfifo: fix file names 2015-04-07 16:40:52 -04:00
Rejeesh Kutty 5f8e9a74ea makefile: updated 2015-04-07 16:32:01 -04:00
Rejeesh Kutty 922ea7fb34 util_sync_reset: removed 2015-04-07 16:28:05 -04:00
Rejeesh Kutty 6d0a2bf64c axi_adcfifo: added 2015-04-07 16:21:39 -04:00