Commit Graph

5929 Commits (f8c82c611d9f200362f442fb49474dad3d6aec49)

Author SHA1 Message Date
cycollineau b93c1e6e90 intel/adi_jesd204: add bonded clock network support (#408)
* jesd204b: add bonding clocks feature (fix for some routing issues)

* intel/adi_jesd204: bonding clock feature invisible in QSYS GUI if number of lanes is less than 6

* intel/adi_jesd204: clock network option renamed according to intel documentation

* intel/adi_jesd204: Hide BONDING_CLOCKS_EN parameter in RX mode

Co-authored-by: István Csomortáni <Csomi@users.noreply.github.com>
2020-01-09 17:45:32 +02:00
Stanca Pop 9497b1cace ad40xx: Remove redundant upscaler IP, Add timing constraints 2020-01-09 11:32:31 +02:00
Arpadi 3235c9189c axi_xcvrlb: added new parameters to IP
added PLL locked reg to axi regmap; IP now recognizez xcvr type
automatically
2020-01-07 16:18:33 +02:00
Laszlo Nagy 9180d4dd39 library/axi_clkgen: Fix second clock output
A typo prevents the usage of second clock output.
2020-01-07 13:21:00 +02:00
István Csomortáni 8db77d8f3a ad_fmclidar1_ebz/README: Add Known Issues section
Add  description of the power-up issue and its solution.
2019-12-20 13:20:42 +02:00
István Csomortáni d4b3a3f640 ad_fmclidar1_ebz/README: A10SOC rework guide 2019-12-18 14:47:00 +02:00
Prasahnt Sivarajah 9ab4c0c783 dac_fmc_ebz: Passthrough GPIO signal for bypass 2019-12-06 11:04:45 +02:00
Prasahnt Sivarajah 8b45d17eb9 dac_fmc_ebz: Only create dummy ports for unused
lanes
2019-12-06 11:04:45 +02:00
Adrian Costina 09ad67bfd7 adrv9009zu11eg: Make the project more parametrizable 2019-12-04 14:59:18 +02:00
Istvan Csomortani 2e4ac278eb ad_fmclidar1_ebz: Add documentation 2019-12-03 18:23:57 +02:00
AndreiGrozav 3c83694755 adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock 2019-12-03 17:27:56 +02:00
Laszlo Nagy a25323b246 util_adcfifo: fix read pointer
Read pointer should be always behind the write pointer except when it
reaches the last memory location where the writer stops.
2019-12-03 17:27:29 +02:00
Laszlo Nagy 82021edffe adi_board.tcl:ad_xcvrcon: do not reorder common control
When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
2019-11-30 12:29:32 +02:00
Laszlo Nagy e6d63ec50d util_pack: Initital support for 32 channels 2019-11-28 16:17:58 +02:00
Laszlo Nagy c2726ceac9 common:vcu118: move system memory to DDR C2
The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
2019-11-28 16:17:44 +02:00
Laszlo Nagy 7612b5d8dd scripts/jesd204.tcl: add support for more lanes and converters for TPLs 2019-11-28 16:17:21 +02:00
Laszlo Nagy 85eabc5a08 jesd204/ad_ip_jesd204_tpl_dac: add support for more lanes and converters 2019-11-28 16:17:21 +02:00
Laszlo Nagy 002f8d8a3e jesd204/ad_ip_jesd204_tpl_adc: add support for more lanes and converters 2019-11-28 16:17:21 +02:00
Laszlo Nagy db573a59b0 jesd204: support for 16 lanes 2019-11-28 16:17:21 +02:00
Adrian Costina 0cb5c0bdaf adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency 2019-11-27 16:27:44 +02:00
Istvan Csomortani c44b4957b5 ad7134_fmc/zed: Fix IO definitions for SDI lines 2019-11-27 10:04:37 +02:00
AndreiGrozav cd5848976e axi_adc_trigger: Change out hold counter width
Chance out hold_counter width form 17 to 20 bits.
Out hold period max ~ 20 ms. Default out hold period 2 ms.
2019-11-26 15:15:58 +00:00
AndreiGrozav 4fdaa7fe12 axi_adc_trigger: Cosmetic change only 2019-11-26 15:15:58 +00:00
AndreiGrozav bdd44e37df axi_adc_trigger: Dynamically set the out pin hold period 2019-11-26 15:15:58 +00:00
Laszlo Nagy 88e80f604e daq3:zcu102: fix GPIO double drive 2019-11-26 14:41:19 +02:00
Laszlo Nagy 10dc090673 .gitignore: add simulation outputs and misc files to the list 2019-11-26 13:43:22 +02:00
Arpadi 4c2a539a96 axi_fan_control: Fixed ip version 2019-11-26 13:33:41 +02:00
Adrian Costina 8c39cf8560 scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections 2019-11-26 12:57:53 +02:00
AndreiGrozav e0813d49b6 axi_adc_trigger: Fix two sample offset
When using a non-maximum sampling rate the data is captured earlier by two
samples.
After the initial trigger jitter fix, a low latency/utilization was
desired(one sample delay for the trigger detection). After adding the
instrument trigger an equal latency between ADC and LA was required, hence the
need for a two sample delay on the trigger path. The delay was implemented
as two clock cycle delays not two sample delays.
This commit fixes this issue and offers a more robust design.
2019-11-25 13:14:18 +00:00
AndreiGrozav d844167850 axi_adc_trigger: Fix trigger jitter
A trigger jitter was added by fix on the external trigger input. It
manifests at input sampling frequencies lower than the maximum frequency.

Added the required reset and CE(valid) signal to the last output
stages of the trigger to obtain the desired functionality for all
sampling rates.
2019-11-25 13:14:18 +00:00
AndreiGrozav 8131c86f75 m2k: Connect the adc_trigger reset 2019-11-25 13:14:18 +00:00
AndreiGrozav ecfa6bd19d axi_logic_analyzer: Add holdoff support 2019-11-25 13:14:18 +00:00
AndreiGrozav ede19a3b3d axi_adc_trigger: Add holdoff support
Add reset pin for holdoff.
2019-11-25 13:14:18 +00:00
Stanca Pop a06c74edc7 fmcjesdadc1: Change rx_div_clk to 125MHz 2019-11-20 10:50:18 +02:00
Sergiu Arpadi 9260979b15 adrv9364: Added sysid to all projects 2019-11-20 10:43:54 +02:00
Sergiu Arpadi 570dae7df6 adrv9361: Added sysid to all projects 2019-11-20 10:43:54 +02:00
Sergiu Arpadi 24b5de4438 sysid: Specified clock interface for input clk 2019-11-20 10:43:54 +02:00
Adrian Costina dfe3258a4f adrv9009zu11eg: Add axi_sysid 2019-11-19 10:29:57 +02:00
Adrian Costina 81d3a9eb66 adrv9009zu11eg: Reduce SPI Clock speed to meet timing 2019-11-19 10:29:57 +02:00
Stanca Pop 4b380fe640 ad7768-1evb: Add coraz7s support 2019-11-15 14:35:00 +02:00
Stanca Pop 40d839df5f coraz7s: Initial commit 2019-11-15 14:35:00 +02:00
AndreiGrozav 514aadb54e m2k: Use dac trigger 2019-11-15 12:23:01 +00:00
AndreiGrozav af2f243b02 axi_dac_interpolate: Add dac trigger feature 2019-11-15 12:23:01 +00:00
Adrian Costina a589a2c7eb adrv9009_zu11eg_som: Change design partitioning
Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
Adrian Costina 39d19ef401 util_adxcvr: Add additional parameters allowing for GTH4 RX 15Gbps rates 2019-11-11 14:46:09 +02:00
Adrian Costina eab1e86544 adrv9364z7020: Rename *box project to *packrf 2019-10-29 16:07:08 +02:00
Adrian Costina de324526e3 adrv9361z7035: Rename *box project to *packrf 2019-10-29 16:07:08 +02:00
AndreiGrozav 64f5a99c63 axi_adc_trigger: Add and 1 extra delay
The extra delay was added on the trigger and data paths to compensate
for the logic analyzer changes.

The extra delay will be also seen on the m2k daisy chain. The
delay between devices will be increased from 3 to 4 samples delay.
2019-10-28 13:13:10 +00:00
AndreiGrozav 10c99562cf axi_logic_analyzer: Add extra reg pipe to avoid latch 2019-10-28 13:13:10 +00:00
AndreiGrozav 6af5d3c358 axi_logic_analyzer: Improve external trigger
Fix external trigger for low sampling rates.
Because the external trigger can be a short pulse at high decimation rates
there is a high chance that the pulse will be missed.
2019-10-28 13:13:10 +00:00