230c579339
common/s10soc: Input ports do not have a current strength property
2020-09-25 12:56:14 +03:00
5644907f75
adi_intel_msg: Dissable "unused TX/RX channel" critical warning for Stratix 10
2020-09-25 12:56:14 +03:00
a738879fa0
ad77681evb: Remove redundant ad_data_clk
2020-09-25 12:20:41 +03:00
144fcc2965
adrv9009: Fix typo for number of samples calculation for observation channel
2020-09-25 11:58:58 +03:00
bde2d1d66d
fmcomms8: zcu102: Leave the SPI constraint at 25 MHz
2020-09-25 11:54:12 +03:00
4d2e05d5dd
fmcomms8: common: In the SPI module, use ad_iobuf instead of a Xilinx primitive
2020-09-25 11:54:12 +03:00
f8c2eb12d4
fmcomms8: zcu102: Remove the test pins, as they are not connected
2020-09-25 11:54:12 +03:00
1e31b9dd97
arradio: Remove unused signals
...
Remove 'ad9361_clk_out' since is not used anymore, fixing in this way 'Warning (21074): Design contains 1 input pin that do not drive logic'
2020-09-23 09:16:48 +03:00
f2f6422751
sysid: Fix board/project name underscore issue
2020-09-17 10:32:58 +03:00
6ae822d42c
cn0506_rmii: Fix no defined clock warnings
2020-09-16 10:57:15 +03:00
49d4286459
cn0540/de10nano: Delete GPIO connection to DRDY
2020-09-15 18:14:23 +03:00
4838ac0ac2
cn0540/coraz7s: Time the SPI interface of AD7768-1
2020-09-15 18:14:23 +03:00
0933949ad7
adv7513: Add initial project for de10nano
2020-09-15 18:14:23 +03:00
043ddbaf9f
cn0540: Add de10nano reference design
2020-09-15 18:14:23 +03:00
ad8d2d225f
de10: Delete redundant base design
2020-09-15 18:14:23 +03:00
fd1c3c7cdd
common/de10nano: Add de10nano base design
2020-09-15 18:14:23 +03:00
6cea8ce777
adi_project_intel: Add de10nano support
2020-09-15 18:14:23 +03:00
40772a8b2c
ad40xx_fmc/zed: Fix constraints, to avoid critical warnings in synthesis
2020-09-15 13:08:39 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
f57643b451
sysid_intel: Added adi_pd_intel.tcl
2020-09-11 15:46:06 +03:00
0152b645a6
m2k: Fix Warnings
...
Fix warnings caused by attempting to set a value to a disabled parameter.
2020-09-11 10:23:26 +03:00
9ee0f09078
daq3:qsys: Activate input pipeline stage for AD9680's JESD interface
2020-09-09 14:15:37 +03:00
c8e0a1ec04
projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
...
To match the Linux default setup.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
61ece1f1e9
s10soc: Insert an additional bridge between DMA and HPS
...
Due to the interface differences between HPS's AXI4 and DMA's AXI4, the
tool will try to automaticaly add some bridges between the two
interface. Unfortunatly it does generate timing issues at the f2sdram0
interface of the HPS instance. By explicitly instantiating an AXI
bridge, these timing issues disappears.
2020-09-09 14:15:37 +03:00
46b6bf8f8a
adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os
2020-09-09 14:15:37 +03:00
5a8f277253
adrv9009/s10soc: Add support for Stratix10 SOC
2020-09-09 14:15:37 +03:00
2b5136db98
scripts/project_intel.mk: Update CLEAN targets
2020-09-09 14:15:37 +03:00
eb8e1142cd
adrv9009/intel: Fix the register address layout
...
The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
2020-09-09 14:15:37 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
...
The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
91b199a907
s10soc: Add new feature for ad_cpu_interconnect
...
If we have a lot of peripherals connected to the CPU's memory interface,
the generated interconnect can grow to much decreasing the timing
margin.
One solution is to group the peripherals by its interface types and
functions and use bridges to connect them to the memory interface.
This commit adds the possibility to insert an Avalon Memory Mapped
bridge when we create the connection between the peripheral and CPU.
Should be used just with Avalaon Memory Mapped interfaces.
2020-09-09 14:15:37 +03:00
f9c4283f45
stratix10soc: Initial commit of base design
...
Note: Currently we have a engineering sample version 2 board.
2020-09-09 14:15:37 +03:00
24090fafd8
adrv9001/zcu102: Loopback VADJ error to the FMC board
2020-08-31 14:14:03 +03:00
d14376547f
adrv9001/zed: Refactor VADJ test in VADJ error
...
The ADRV9002 uses in the digital interface 1.8V, however the Zed VADJ is
selectable by a jumper can go up to 3.3V . Voltage levels higher than 1.8V
are detected by the EVAL-ADRV9002 board, asserting the VADJ_ERR pin.
If VADJ error is set high keep all drivers in high-z state and signalize
it to the software layer through a gpio line.
2020-08-31 14:14:03 +03:00
72f916fcf5
adrv9001/zcu102: Update interface signal names based on direction
...
Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
a212ad6e58
adrv9001/zed: Update interface signal names based on direction
...
Let the names of signals from source synchronous interface match the
direction of the signals.
2020-08-28 13:23:00 +03:00
eb2f211d30
scripts/intel: Add message severity definition file
2020-08-25 14:46:52 +03:00
9c4df588bb
fmcomms2: a10soc remove project
...
Starting from Quartus 18.1 the project won't build as LVDS SERDES needs to be
driven by a dedicated reference clock pin and A10SOC doesn't have dedicated pins
routed at the _CC FMC location.
Prior to version 18.0 this was reported as a critical warning.
See https://community.intel.com/t5/Intel-Quartus-Prime-Software/LVDS-SERDES-reference-clock-enforcement-change-in-18-1/td-p/196078
2020-08-25 14:19:48 +03:00
118e1f9e8b
adrv9001/zed: Initial support for Zed
...
CMOS only support for ADRV9001 on ZedBoard
2020-08-24 17:49:12 +03:00
b27f3ac18f
adrv9001:zcu102: Initial version
...
Generic project that supports CMOS or LVDS interface for the ADRV9001 transceiver.
2020-08-24 17:49:12 +03:00
d8c98c9904
cn0540/coraz7s: Relax timing in SPI Engine
2020-08-24 16:45:02 +03:00
fa0b39fa20
adi_project_intel: Update QSYS generation
...
In Quartus Prime in place of the set_domain_assignment command, the
set_interconnect_requirement command is used.
2020-08-17 12:02:49 +03:00
b54effc9c9
daq2/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
fb7da01498
adrv9371x/a10gx: Set optimization mode to aggressive performance
2020-08-17 10:43:03 +03:00
738f7af23b
ad40xx_fmc: SDI delay should be set to 1
...
In general we have to add a delay of half SCLK cycle.
(latch the MISO on the next consecutive SCLK edge)
2020-08-13 10:01:16 +03:00
4766d01915
m2k: Update constraints
2020-08-13 07:01:19 +03:00
4d39a3595f
m2k: Connect signals for instrument sync
2020-08-13 07:01:19 +03:00
f3b69c15c9
scripts/intel: Update version check
2020-08-12 10:33:29 +03:00
218f45a0df
scripts/intel: Set supported Quartus version to 19.3
2020-08-12 10:33:29 +03:00
62eb5a067d
fmcomms2/a10soc: Unused outputs should be left hanging
2020-08-11 10:14:18 +03:00
a66029aef3
adrv9009/a10gx: Delete redundant timing constraints
2020-08-11 10:14:18 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
...
All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
f1a0946a5d
daq3: Delete redundant timing constraint
...
Delete none generic timing constarints related to the memory interface.
Set optimization mode to default.
2020-08-11 10:14:18 +03:00
1c907b9248
daq2/a10gx: Use the default optimization mode
2020-08-11 10:14:18 +03:00
9043f3737b
Revert "a10gx: Optimise the base design"
...
This reverts commit 9afc871b70
2020-08-11 10:14:18 +03:00
4af0c98c56
a10gx: Fix exceptionSlave interface definition for HPS
2020-08-11 10:14:18 +03:00
5ba3448987
scripts/project-intel: Update CLEAN target
2020-08-11 10:14:18 +03:00
0b51c474a1
a10gx: Add a Avalon Pipeline Bridge between EMIF and DMA's
2020-08-11 10:14:18 +03:00
6d19041b21
dac_fmc_ebz: QPRO is using apply_instance_preset
2020-08-11 10:14:18 +03:00
0de5039b96
avl_dacfifo: add_intance command must have a version attribute
2020-08-11 10:14:18 +03:00
8fd1ad64d6
quartus: Increase tool version to 19.2
2020-08-11 10:14:18 +03:00
f3142a6a7a
adi_project_intel: set_interconnect_requirment command is deprecated
...
Use set_domain_assignment to set up the maximum pipeline stages for the
main interconnect.
2020-08-11 10:14:18 +03:00
a39fa831d0
ad9371:a10gx: Relax interconnect requirements
2020-08-11 10:14:18 +03:00
7e22f91429
adrv9371:a10gx: Remove constraint from DDR
2020-08-11 10:14:18 +03:00
359e5d94ec
a10gx: Remove constraint from eth_ref_clk
2020-08-11 10:14:18 +03:00
967a138d0f
adi_project_intel: Add support for Quartus Pro
...
By defualt the supported tool chain is Quartus PRO. If you want to
build the project with Quartus Standard, you need to define an environment
variable called QUARTUS_PRO_ISUSED with the value 0. (e.g. export
QUARTUS_PRO_ISUSED=0 )
Note: Not all projects going to build on Quartus Standard, you should
fix the errors if there is any.
2020-08-11 10:14:18 +03:00
054193e083
adi_project_intel: Delete all MESSAGE_DISABLE assignment
...
These kind of assignments should be placed into file like
~/projects/scripts/adi_xilinx_msg.tcl
2020-08-11 10:14:18 +03:00
4ca1311d57
quartus_pro: Global assignment ENABLE_ADVANCED_IO_TIMING is not supported
2020-08-11 10:14:18 +03:00
8d6b8fc631
Add cn0506_rmii/zcu102 support on revB
2020-08-10 18:32:44 +03:00
7e96514230
Add cn0506_rmii/zc706 support on revB
2020-08-10 18:32:44 +03:00
321b82398b
Add cn0506_rmii/zed support on revB
2020-08-10 18:32:44 +03:00
6c2b1b1634
fmcomms5/zc702: Fix the sys_dma_clk connections
2020-06-19 12:53:18 +03:00
137c31db1d
daq2/xilinx: Update project to use generic JESD204 TPL
2020-06-18 15:45:19 +03:00
299273f5a1
daq2/intel: Update project to use generic JESD204B TPL
2020-06-18 15:45:19 +03:00
847f0f22e6
cn0540: Fix typo
2020-06-04 18:38:14 +03:00
193fce338d
cn0540: Initial commit
2020-05-28 18:49:35 +03:00
03ab28d7bf
ad77681evb: Remove coraz7s project
2020-05-28 18:49:35 +03:00
71d500bdd4
adrv9009/intel: Use generic TPL cores
2020-05-26 16:22:30 +03:00
9c8190f709
adi_project_xilinx.tcl: discover all timing failures
...
Look for an overall indicator of timing failure.
Create critical warning if timing is failed.
2020-05-26 14:47:38 +03:00
47a97aac7c
adrv9371x/intel: Update project to use generic JESD204B TPL
2020-05-25 11:55:40 +03:00
e8f6523197
ad9081_fmca_ebz: adapt to renamed tpl core
2020-05-20 19:08:25 +03:00
db6af63583
scripts/adi_env.tcl: print in logs system variables are used
2020-05-20 19:07:23 +03:00
e7600eb552
ad7616_sdz: Fix the project, after SDI ports were merged
...
Update the project to support the SDI port merge patch: 4d54c7e
2020-05-20 11:44:22 +03:00
4d54c7e2d6
spi_engine_execution: Merge the SDI lines into one vector
...
This modification will help to support multiple SPI engine
execution setups (e.g. different NUM_OF_SDI) for the same project.
2020-05-19 09:28:02 +03:00
6535e5b2ba
scripts/xilinx: Version mismatch is upgraded to ERROR
...
There is a major compatibility issue between 2019.1 and 2019.2.
The file system_top.hdf got a different file extention. This will
cause a compilation failer in the end of the build. To save time
and fail earlier, upgrade the version mismatch message to ERROR.
If user still wants to build a branch with different tool version
the variable ADI_IGNORE_VERSION_CHECK should be set to 1.
2020-05-15 12:16:35 +03:00
32eeedb660
makefile: Update makefiles
2020-05-07 08:41:49 +01:00
cbb23c7b67
ad9081_fmca_ebz: fix Xilinx PHY resets
...
Avoid clock domain crossing on resets.
2020-04-23 17:21:05 +03:00
e112a03d85
ad9081_fmca_ebz: Whitespace cleanup
...
Clear extra lines and whitespaces at end of lines.
2020-04-23 17:21:05 +03:00
7df4caf8b0
ad9081_fmca_ebz: Added parameter description
...
Add parameter description to project and common block design file
2020-04-23 17:21:05 +03:00
e433d3f808
ad9081_fmca_ebz: expose PLL selection as a parameter
...
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
0 - CPLL
1 - QPLL0
2 - QPLL1
Since the selection of line rate is available from the project also the
PLL selection must be exposed.
2020-04-23 17:21:05 +03:00
b774e1ca7d
ad9081_fmca_ebz: enable IQ rotation
2020-04-03 11:16:37 +03:00
4684dc03ce
dac_fmc_ebz/a10soc: Use balanced optimization mode
...
Always a good idea to start from default, and change optimization mode
of the tool if it's strict necessary.
2020-03-17 17:25:02 +00:00
253a8cb6ee
dac_fmc_ebz/a10soc: Tool expect that all config parameters exists on top entity
2020-03-17 17:25:02 +00:00
522aacf6d8
ad_fmclidar1_ebz/a10soc: Fix AFE's I2C interface
...
The AFE's I2C interface should be pin-multiplexed to the FPGA. Also, add
a bidirectional IO buffer for the interface, and make sure it has weak
pull-up resistors.
2020-03-17 07:27:49 +00:00
19b7986486
fmcomms8: Fix SPI timing
...
The maximum SPI rate set to 10MHz
2020-03-16 13:26:20 +02:00
fde79a2272
ad_fmclidar1_ebz: Fix AFE's SPI polarity
2020-03-10 16:37:18 +00:00
b1f62f09ac
ad9081_fmca_ebz:vcu118: initial version
...
Use over-writable parameters from the environment.
e.g.
make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=12.375 REF_CLK_RATE=375 RX_JESD_L=4 TX_JESD_L=4
make JESD_MODE=64B66B RX_RATE=16.22016 TX_RATE=16.22016 REF_CLK_RATE=245.76 RX_JESD_M=8 RX_JESD_L=2 TX_JESD_M=16 TX_JESD_L=4
make JESD_MODE=8B10B RX_JESD_L=4 RX_JESD_M=8 TX_JESD_L=4 TX_JESD_M=8
2020-03-10 18:19:03 +02:00
f3a7fd8b0d
ad9081_fmca_ebz:zcu102: initial version
2020-03-10 18:19:03 +02:00
f3630dd95b
ad9081_fmca_ebz: common block design
...
Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
2020-03-10 18:19:03 +02:00
1f7671cb36
scripts/adi_env.tcl: helper function for environment variables
...
Ease the access of the environment variables.
2020-03-10 18:19:03 +02:00
fad52175d1
fmcomms8: Fix spi connection
2020-03-06 16:07:02 +02:00
50d904934a
fmcomms8: Changed the interrupt addresses to be similar with adrv9009zu11eg project
2020-03-06 16:07:02 +02:00
e1353d5291
m2k: use DMA streaming interface
...
The previous mechanism was "probing" the DMAs for valid data. Better said,
each interpolation channel enabled it's DMA until a valid data was received,
then it disabled the DMA read and waited for the adjacent channel(DMA) to
receive a valid data. Only when for both channels had valid data on the
DMAs interfaces was the transmission started. This added an undesired and
redundant complexity to the interpolation channels. Furthermore, for continuous
transmission, using the above mechanism lead to a fixed phase(sample)
shift between the two channels at each start.
By using the streaming mechanism the interface is simplified and the
above problems are solved.
2020-03-06 15:57:43 +02:00
dd47e30431
ad7768_evb_sync: Fixed sync issue
...
fixed sync inside ad7768_if module;
2020-03-04 18:21:55 +02:00
35412c81a9
dac_fmc_ebz: drive spi_en pin automatically based on FMC board selected
...
spi_en is active ...
... high for AD9135-FMC-EBZ, AD9136-FMC-EBZ, AD9144-FMC-EBZ,
... low for AD9171-FMC-EBZ, AD9172-FMC-EBZ, AD9173-FMC-EBZ
2020-03-03 15:49:30 +02:00
ef15757d9e
common:vcu118: support for plddr4 adc and dac fifo
...
Use 1GB from the DDR4 for either ADC or DAC sample buffering.
Max theoretical bandwidth of 19.2 GB/s
2020-03-03 15:49:11 +02:00
48a91796e2
ad77681evb: Set spi_clk to 40MHz ( #435 )
2020-02-24 12:55:06 +02:00
37188b01d8
fmcomms2:a10soc: use non DPA mode
2020-02-24 11:31:01 +02:00
96b7b3fa5f
fmcomms2: Add support for a10soc
...
Because fmcomms2 was not supported on a Intel carriers the
fmcomms2_qsys.tcl file got outdated.
The arradio project has the same hdl design. Hence the update is
merely a copy of the arradio_qsys.tcl with small changes.
2020-02-24 11:31:01 +02:00
2bca2e156c
cn0506_rgmii: Fix no clock defined warnings
...
This commit fixes the critical warning regarding the missing clock
definitions.
- Defined MDC(MDIO) clocks
- Set false path on(to) the ps8 MDIO input pins. There are synchronization
stages in the GMII to RGMII converter for the CDC between the 375M refclk
and 2.5M MDC clock domains.
2020-02-21 18:22:49 +02:00
6d91e2e54f
coraz7s_fix: Tied drdy to gpio
...
removed IOB attribute for drdy
2020-02-18 13:24:43 +02:00
501abfd53a
common/coraz7s: Fixed ethernet issue
...
fixed coraz7s preset; cleaned up lines which generated warnings
2020-02-18 13:24:43 +02:00
c4b94fc564
adrv9009zu11eg: Add S JESD204 parameter for the projects
2020-02-18 11:19:02 +02:00
645696e5b4
adrv9009zu11eg: Extend SPI connection to the PL HD PINS expansion
2020-02-18 11:19:02 +02:00
d2817863a1
adrv9009zu11eg: Add FMCOMMS8 support
2020-02-18 11:19:02 +02:00
29f18e501e
adrv9009zu11eg: Cleanup bd file
2020-02-18 11:19:02 +02:00
3192807f22
adi_project_xilinx: Fixed variable name
2020-02-14 11:22:46 +02:00
c5e03eb196
adi_project_xilinx: Added power analysis procedure
2020-02-14 11:22:46 +02:00
74fc68d4c3
axi_fan_control: Changed temperature thresholds to registers
...
implemented mux for temp reading either from internal or external
source; updated regmap; added param to identify source for temp
information; updated tacho measurements; added AVG_POW param used
for tacho measuremet average useful for simulations; defaults for
tacho measurements changed to params and added registers; added
prescaler for fsm control, FSM updated; changed register write
process; connected INTERNAL_SYSMONE to regmap, value can now be
read by software;
2020-02-14 11:21:12 +02:00
78a1e54a33
adi_project_xilinx.tcl: Generate resource utilization for IPs
2020-02-13 11:33:02 +02:00
46a413d9a5
dac_fmc_ebz/common/config.tcl: fix typo
2020-02-13 11:32:38 +02:00
e51d9372cd
fmcomms8: ZCU102: Added DAC FIFO
2020-02-10 11:23:52 +02:00
016a1d540d
fmcomms8: ZCU102: Initial commit
2020-02-10 11:23:52 +02:00
10a808b504
ad9208_dual_ebz/vcu118: remove GTY prefix from parameters
2020-02-10 09:48:17 +02:00
05c20af988
Merge pull request #430 from analogdevicesinc/update_tcl
...
Rename projects for consistency
2020-02-06 16:32:40 +02:00
e00ee136f6
cn0506_mii Updates for Rev B board
...
Because of the rmii mode requirements(external 50MHz clock) the
board will have the rx_err signal replaced on the FMC connector with the
50MHz external clock (D08/D20).
The rx_er will be shifted to the D9/D21 pins.
2020-02-03 11:20:18 +02:00
b3e475cb8b
ad_fmclidar1_ebz: Update the IO constraints to revB
...
The IO location of the laser_driver_otw_n was moved from FMC_HPC_LA27_N
to FMC_HPC_LA31 (laser_gpio[12]).
laser_gpio[11:0] assignments were shifted with one bit to MSB, and laser_gpio[0]
got the old location of the laser_driver_otw_n.
2020-01-31 18:47:37 +02:00
135538b521
adi_project: Fixed kcu105 board file selection
2020-01-16 17:16:58 +02:00
db5e21cfb9
pluto revC: Add second RF channel
...
-add second RF channel (without fir filters)
-use a more generic instantiation of the fir filters
-add util_cpack2 and util_upack2
2020-01-16 11:40:28 +02:00
f9c8ff26cf
pluto rev C hardware updates
...
-connect axi_spi to board GPIOs
-connect axi IIC to board GPIOs
MIO49 SPI_CS (PS MIO49)
L10P SPI_MOSI (AXI_SPI)
L12N SPI_MISO (AXI_SPI)
L24N SPI_CLK (AXI_SPI)
L7N iic_sda (AXI_IIC)
L9N iic_scl (AXI_IIC)
2020-01-16 11:40:28 +02:00
e773b22087
adi_project: Updated board files version selection
...
vivado will automatically select the latest version for a given board
2020-01-14 17:16:01 +02:00
fcf7bb035a
ad40xx: Fix data_width definition
2020-01-14 15:24:43 +02:00
d86fbb2a08
adi_board: fixed ddr memory mapping for microblaze projects
2020-01-13 12:25:23 +02:00
34ea5efdff
adi_project_xilinx: Use the latest board files
2020-01-13 12:25:23 +02:00
adfeb435a4
scripts: Update Vivado version to 2019.1
2020-01-13 12:25:23 +02:00
fa259c7975
ad40xx: Fix a typo
2020-01-10 10:20:06 +02:00
9497b1cace
ad40xx: Remove redundant upscaler IP, Add timing constraints
2020-01-09 11:32:31 +02:00
8db77d8f3a
ad_fmclidar1_ebz/README: Add Known Issues section
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Add description of the power-up issue and its solution.
2019-12-20 13:20:42 +02:00
d4b3a3f640
ad_fmclidar1_ebz/README: A10SOC rework guide
2019-12-18 14:47:00 +02:00
9ab4c0c783
dac_fmc_ebz: Passthrough GPIO signal for bypass
2019-12-06 11:04:45 +02:00
8b45d17eb9
dac_fmc_ebz: Only create dummy ports for unused
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lanes
2019-12-06 11:04:45 +02:00
09ad67bfd7
adrv9009zu11eg: Make the project more parametrizable
2019-12-04 14:59:18 +02:00
2e4ac278eb
ad_fmclidar1_ebz: Add documentation
2019-12-03 18:23:57 +02:00
3c83694755
adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock
2019-12-03 17:27:56 +02:00
82021edffe
adi_board.tcl:ad_xcvrcon: do not reorder common control
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When channels are not swapped in groups of four but are completely out of order
the common control channel can't be reordered based on the index of the
channel.
2019-11-30 12:29:32 +02:00
c2726ceac9
common:vcu118: move system memory to DDR C2
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The DDR controller for C2 for is much closer to the transceivers which
connect to the FMCp connector so designs does not have to span over all
three SLRs just over two reducing implementation and timing closure effort.
2019-11-28 16:17:44 +02:00
0cb5c0bdaf
adv9009zu11eg: Update FPGA to -2. Update DDR4 clock frequency
2019-11-27 16:27:44 +02:00
c44b4957b5
ad7134_fmc/zed: Fix IO definitions for SDI lines
2019-11-27 10:04:37 +02:00
88e80f604e
daq3:zcu102: fix GPIO double drive
2019-11-26 14:41:19 +02:00
8c39cf8560
scripts: adi_board.tcl: Update the axi_adxcvr to util_adxcvr connections
2019-11-26 12:57:53 +02:00
8131c86f75
m2k: Connect the adc_trigger reset
2019-11-25 13:14:18 +00:00
a06c74edc7
fmcjesdadc1: Change rx_div_clk to 125MHz
2019-11-20 10:50:18 +02:00
9260979b15
adrv9364: Added sysid to all projects
2019-11-20 10:43:54 +02:00
570dae7df6
adrv9361: Added sysid to all projects
2019-11-20 10:43:54 +02:00
dfe3258a4f
adrv9009zu11eg: Add axi_sysid
2019-11-19 10:29:57 +02:00
81d3a9eb66
adrv9009zu11eg: Reduce SPI Clock speed to meet timing
2019-11-19 10:29:57 +02:00
4b380fe640
ad7768-1evb: Add coraz7s support
2019-11-15 14:35:00 +02:00
40d839df5f
coraz7s: Initial commit
2019-11-15 14:35:00 +02:00
514aadb54e
m2k: Use dac trigger
2019-11-15 12:23:01 +00:00
a589a2c7eb
adrv9009_zu11eg_som: Change design partitioning
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Create a structure similar with ADRV936x projects
2019-11-14 15:25:23 +02:00
eab1e86544
adrv9364z7020: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
de324526e3
adrv9361z7035: Rename *box project to *packrf
2019-10-29 16:07:08 +02:00
fba7cac0c6
ad7768-1evb: Remove ADC2, update spi engine framework
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The second ADC was removed from the project, as the EV-AD7768-1FMCZ evaluation
board contains only one ADC. Therefore, all the IPs related to the
second ADC have been removed, too.
The data width supported by the spi IPs has been changed from 8 bits to
32 bits, therefore the axis_upscaler(util_axis_upscale_v1_0) and the
m_axis_samples_24(AXI4-Stream Data Width Converter) are no more necessary,
so they have been removed from the design.
The 24 bits width data transfer between the s_axis of axi_ad77681_dma
(AXI DMA Controller) and the offload_sdi of the spi_engine_offload is now made
directly.
2019-10-28 12:00:23 +02:00
4941d89fff
cn0506_mii: Add support on a10soc
2019-10-18 19:09:04 +03:00
fbb3a154ff
cn0506_mii: Add support on zcu102
2019-10-18 19:09:04 +03:00
3cb2392711
cn0506_mii: Add support on zc706
2019-10-18 19:09:04 +03:00
e98951d282
cn0506_mii: Add support on zed
2019-10-18 19:09:04 +03:00
8202c0025c
cn0506_mii: Common design initial commit
2019-10-18 19:09:04 +03:00
9323f4193c
m2k: Clean old interrupt connection style
2019-10-18 18:28:01 +03:00
a4547a32b6
pluto: Clean old interrupt connections style
2019-10-18 18:28:01 +03:00
fd4d32c408
projects/scripts/*xilinx*: Generate report utilization extra files
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Add commands to generate one extra file with resource utilization, in CSV format.
New commands executes only if ADI_GENERATE_UTILIZATION env variable is set.
2019-10-18 13:42:34 +03:00
5a4726b356
adrv9364z7020: Fix interrupt concatenation
2019-10-17 15:09:48 +03:00
f0f314f24b
adrv9361z7035: Fix interrupt concatenation
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None functional change, main goal is to increase consistancy in our
code base.
2019-10-17 15:09:48 +03:00
80333573c7
ad_fmclidar1_ebz/zcu102: Fix SYSREF input delay constraint
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Add one clock cycle input delay for the SYSREF input,
to compensate the high propegation delay of device_clk_BUFG.
2019-10-17 09:59:23 +03:00
03bec4b49c
ad_fmclidar1_ebz: Interchange SYSREF and DEV_CLK ports location
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In ZCU102 LA01_CC_P|N are connected to regional clock, but in order to
receive a device clock properly we have to use pin which is connected
to a global clock buffer. Luckily SYSREF is connected to global clock
pin; swap to port to receive the device clock correctly.
Also, swap the ports in both ZC706 and A10SOC carriers.
2019-10-17 09:59:23 +03:00
2cabf8d224
ad_fmclidar1_ebz: Move afe_iic definition to system_bd.tcl
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In order to prevent platform specific variable usage in the common tcl
script, move the AFE I2C interface definition to system_bd.tcl
2019-10-17 09:59:23 +03:00
b3e1cd2a15
ad_fmclidar1_ebz: Add support for ZCU102
2019-10-17 09:59:23 +03:00
3084a5d9aa
ad_fmclidar1_ebz/a10soc: Fix the comment about the carrier re-work
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The project is using the FMCA connector of the board. Make sure that all
the carrier re-work is related to the FMCA connector.
2019-10-17 09:58:52 +03:00
12c474ba13
ad7134: Change maximum data width from 24b to 32b
2019-10-16 17:35:24 +03:00
3c46cc9347
dac_fmc_ebz: Add project info to sys_id
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Add project device and mode info to sys_id custom string
2019-10-15 17:08:53 +03:00
58b846faae
dac_fmc_ebz: Add build time config option
2019-10-15 17:08:53 +03:00
e22016de4c
adrv9371/daq2/daq3:kcu105: patch GTH3 CPLL parameters
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Update GTH3 parameters according to a 10Gbps link from the Transceiver
Wizard.
2019-10-08 10:38:46 +03:00
8895b08eb1
adrv9009_zu11eg_som: i2s mclk fix
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mclk now generated by ps not axi clkgen ip. ADAU1761 expects a free
running clock and the i2s driver was switching the axi clkgen ip off
which was causing issues.
2019-10-03 17:30:57 +03:00
2344778dd8
ad_fmclidar1_ebz/a10soc: Initial commit
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Add initial support for Arria 10 SOC carrier.
2019-10-02 15:32:17 +03:00
23d29e7a15
a10soc_system_qsys: sys_dma_clk clock_source inherit its clock frequency from its source
2019-10-02 15:32:17 +03:00
af94487f57
adi_project_intel: Enable HPS internal timing
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It's recommended to use this global assignment so the tool can make a
more in-depth timing analysis.
2019-10-02 15:32:17 +03:00
bc2f916dfc
a10soc: Synchronize resets to the reset source
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Resets de-assertion should be synchronized to its associated clock.
2019-10-02 15:32:17 +03:00
9c9ce928d8
Merge pull request #346 from analogdevicesinc/spi_engine_trigger_update
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spi_engine: Update pulse generation
2019-10-02 14:42:41 +03:00
75d263afc5
adi_project_xilinx: Add constraint files to constr_1 file set
2019-09-27 18:21:25 +03:00
64e54fda8d
fmcomms5: remove clock skew handling
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Use SSI clock from master as SSI clock of slave.
2019-09-27 17:52:10 +03:00
994bb6d0cf
adaq7980: Software configurable trigger
2019-09-27 17:02:52 +03:00
b174333fa2
project-xilinx.mk: Clean generated file by sysid
2019-09-27 13:16:19 +03:00
7a685dd443
cn0506_rgmii/zcu102: Fix README typo
2019-09-26 16:33:45 +03:00
442b38033a
sys_id: added catch to git status check
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made error checking more general
2019-09-26 16:26:02 +03:00
447434ace0
cn0506_rgmii: Add support for a10soc
2019-09-20 18:03:27 +03:00
1138c48270
cn0506_rgmii: Add support for zcu102
2019-09-20 18:03:27 +03:00
f4f547715e
cn0506_rgmii: Add support for zc706
2019-09-20 18:03:27 +03:00
98fba87d8f
cn0506_rgmii: Add support for zed
2019-09-20 18:03:27 +03:00
afd9420dab
cn0506_rgmii: base design initial commit
2019-09-20 18:03:27 +03:00
7c3b4a5c73
ad9208_dual_ebz: Cleanup workarounds
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Cleanup placement constraints and let the tool have more freedom to
place and route the design. This is possible only after balancing the
memory and system clocks.
2019-09-16 10:00:14 +03:00
b7d48b8c74
common/vcu118: Balance clocks
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Minimize skew on synchronous CDC timing paths between clocks originating
from the same MMCM source. (sys_mem_clk and sys_cpu_clk)
This is required mostly by the smart interconnect.
The CLOCK_DELAY_GROUP property must be applied directly to the output net of BUFGs.
2019-09-16 10:00:14 +03:00
Istvan Csomortani
Stanca Pop
Adrian Costina
stefan.raus
sergiu arpadi
AndreiGrozav
Stanca.Pop
Dragos Bogdan
Laszlo Nagy
StancaPop
István Csomortáni
Prasahnt Sivarajah