70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
aa0ea252ec
fmcomms5: constrain ref clock
2019-05-30 14:55:11 +03:00
4b13274c55
ad9361/all/system_constr.xdc: remove manual clock definition
...
Having a clock assigned manually to the clk output pin of the axi_ad9361
let the Vivado timing engine to not ignore the clock insertion delay when
analyzing paths between clk_0 and the manually created clock that has
the same source (clk_0), resulting in timing failure.
2019-04-12 10:48:50 +03:00
3bc9df4c51
fmcomms5: Fixed the wornings created by TDD missing connections to axi_ad9361 core
2016-12-07 21:43:19 +02:00
0ade2a5f67
fmcomms5: Updated project to vivado 2014.2. Updated interrupt system. Fixed constraints
2014-11-07 13:45:15 +02:00
e9f8c0fb5f
fmcomms5: ZC706 modified constraints for linux build machines
2014-08-01 18:09:55 +03:00
a68f634de9
fmcomms5: Added resetb for the second AD9361
2014-07-24 17:31:30 +03:00
7e6b4ea9d0
fmcomms5: ignore only common clock to external clocks
2014-05-19 20:38:41 -04:00
9a36075324
moved fmcomms5
2014-05-19 13:49:49 -04:00
Istvan Csomortani
Laszlo Nagy
AndreiGrozav
Adrian Costina
Rejeesh Kutty