Commit Graph

14 Commits (f8c82c611d9f200362f442fb49474dad3d6aec49)

Author SHA1 Message Date
Adrian Costina 9093a8c428 library: Move ad_iobuf to the common library, as it's not Xilinx specific
Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
Istvan Csomortani a589753d92 project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl 2019-06-29 06:53:51 +03:00
Istvan Csomortani 43725429ac adi_project: Rename the process adi_project_xilinx to adi_project 2019-06-29 06:53:51 +03:00
Istvan Csomortani bbb72d2c7e fmcomms2/zc702: Modify implementation strategy to Performance Exlpore
When we improve timing by modifying the implementation strategies,
the general rule of thumb is "less is always more".

Timing did not fail in synthesis, so we leaving the synthesis
strategy in default.
After several parallel runs with various strategies, the
"Performance_Explore" strategy gave the best result for
implementation.
2018-09-27 11:46:12 +03:00
AndreiGrozav 9877862517 fmcomms2/zc702: Fix implementation timing issues
Changed the tool strategies for synthesis and implementation.
2018-04-11 15:09:54 +03:00
Rejeesh Kutty 4ef784b609 fmcomms2/zc702- pmod1 udc, pmod2 gpio 2017-08-09 14:08:47 -04:00
Adrian Costina b7ca17f02b scripts: Change adi_project_create to adi_project_xilinx for creating xilinx projects 2017-06-07 12:06:50 +03:00
Rejeesh Kutty 0ae79ca7ac move/rename - delay script belongs to ad9361 2017-03-10 12:44:32 -05:00
Rejeesh Kutty 452e5e5ce0 fmcomms2- add delay reporting for iodelay 2017-03-09 15:29:15 -05:00
AndreiGrozav b0eff57b0f fmcomms2/zc702: Fix critical warnings 2016-12-08 19:54:52 +02:00
Istvan Csomortani df36902713 lib_refactoring: Fix path of the IO macros 2016-08-08 15:07:19 +03:00
Adrian Costina 70e1d13a7b fmcomms2: Updated project 2015-03-13 12:49:17 +02:00
Istvan Csomortani ca4c961891 fmcomms2: Use ad_iobuf instance on system_top
Use ad_iobuf instance on system top, instead of separate IOBUF instances.
2014-10-10 18:45:39 +03:00
ATofan 2c898bf3a2 Added ZC706, ZC702 and ZED FMCOMMS2 Vivado Project
ZC706 runs rx_clk at 250 MHz.
ZC702 and ZED run rx_clk at 200 MHz due to slower fabric.
The ZC702 and ZED projects need init_user in the boot procedure in order for the HP Ports to work correctly.
Both DDS and DMA mode work.
2014-03-18 15:27:42 +02:00