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21 Commits (f8c82c611d9f200362f442fb49474dad3d6aec49)

Author SHA1 Message Date
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 2178191610 ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine 
Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
Laszlo Nagy cf7f45ffcc ad9081_fmca_ebz: Fix for F=8 2021-05-14 15:39:40 +03:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects 
The block design expects a lane rate to be set in the system project.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 693c002668 ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR 
Remove Xilinx PHY and simplify project
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d92f925b06 ad9081_fmca_ebz: Disable XBAR from DAC TPL 2021-05-14 15:39:40 +03:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Laszlo Nagy 6b13b32f24 ad9081_fmca_ebz: Workaround DMA bug when bus size equals max burst size 2021-03-04 11:13:29 +02:00
Laszlo Nagy ddd8a14790 ad9081_fmca_ebz: Remove system reset from Xilinx PHY 
Reset in device clock domain caused timing failures.
Since link reconfiguration is not supported the reset is not required.
 2021-02-05 15:24:15 +02:00
Laszlo Nagy af3e1c7003 ad9081_fmca_ebz/a10soc: Np 12 support 2021-02-05 15:24:15 +02:00
Laszlo Nagy d0f8a81b2f ad9081_fmca_ebz: Np 12 support 
204B functional
204C functional
 2021-02-05 15:24:15 +02:00
Laszlo Nagy 0fd5590e56 ad9081_fmca_ebz: a10soc: Initial version 
Parametrizable project with default profile of:

  M=8 L=4 SampleRate=250 MSPS
  LaneRate=10 Gbps
 2021-02-05 10:24:59 +02:00
Laszlo Nagy 3dd370a27c ad9081_fmca_ebz: enable xbar in DAC TPL 2020-11-27 09:45:11 +02:00
Laszlo Nagy e9f319e3d7 ad9081_fmca_ebz: HP0 is already initialized in ZC706 
On carriers like ZC706 the HP0 interconnect is in already in use so it must
not be initialized here.
 2020-11-12 15:46:27 +02:00
Laszlo Nagy e8f6523197 ad9081_fmca_ebz: adapt to renamed tpl core 2020-05-20 19:08:25 +03:00
Laszlo Nagy cbb23c7b67 ad9081_fmca_ebz: fix Xilinx PHY resets 
Avoid clock domain crossing on resets.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e112a03d85 ad9081_fmca_ebz: Whitespace cleanup 
Clear extra lines and whitespaces at end of lines.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy 7df4caf8b0 ad9081_fmca_ebz: Added parameter description 
Add parameter description to project and common block design file
 2020-04-23 17:21:05 +03:00
Laszlo Nagy e433d3f808 ad9081_fmca_ebz: expose PLL selection as a parameter 
On the Xilinx PHY the available PLL options depends on the lane rate.
Encoding is:
  0 - CPLL
  1 - QPLL0
  2 - QPLL1

Since the selection of line rate is available from the project also the
PLL selection must be exposed.
 2020-04-23 17:21:05 +03:00
Laszlo Nagy b774e1ca7d ad9081_fmca_ebz: enable IQ rotation 2020-04-03 11:16:37 +03:00
Laszlo Nagy f3630dd95b ad9081_fmca_ebz: common block design 
Parametrizable block design with selectable JESD physical layer between
Xilinx Phy and ad_utilxcvr.
 2020-03-10 18:19:03 +02:00