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3132 Commits (f8c82c611d9f200362f442fb49474dad3d6aec49)

Author SHA1 Message Date
stefan.raus 1f24344620 Update Quartus version to 20.4 
Update quartus compilation tools from 20.1 to 20.4.
Remove hardcoded version from axi_adrv9001 ip.
 2021-08-12 11:15:01 +03:00
AndreiGrozav b1d2a069e8 adi_make: Update bin build flow for 2020.1 tools 
The 2020.1 Xilinx tools have a different tcl procedures to build the boot.bin
file.
This commit updates the adi_make tcl flow for the new tools. The new
process is not backwards compatible with tools older than 2020 version.
 2021-08-10 17:44:30 +03:00
David Winter e9e278c898 ad9081_fmca_ebz: Remove bypass gpio 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
David Winter 2178191610 ad9081_fmca_ebz: Switch util_dacfifo to data_offload engine 
Memory requirements are the same as with the dacfifo (1 MiB).

Signed-off-by: David Winter <david.winter@analog.com>
 2021-08-06 11:55:24 +03:00
Istvan Csomortani 564ef77588 data_offload: Calculate AXI_ADDRESS_LIMIT automatically 2021-08-06 11:55:24 +03:00
Istvan Csomortani c82b0fb420 data_offload: Delete fifo_dst_rlast 2021-08-06 11:55:24 +03:00
Istvan Csomortani 4026f2d414 daq2/zc706: PL DDR size is 1GByte 2021-08-06 11:55:24 +03:00
Istvan Csomortani 703cc8a17e data_offload_bd: Calculate the address limit from the address width 2021-08-06 11:55:24 +03:00
Istvan Csomortani 78999e154e adrv9009zu11eg: Integrate data_offload 2021-08-06 11:55:24 +03:00
Istvan Csomortani dc910420bd daq2: Integrate data_offload 2021-08-06 11:55:24 +03:00
Istvan Csomortani 4c03580156 data_offload: Add integration process for Xilinx carriers 2021-08-06 11:55:24 +03:00
Adrian Costina f2ca956d23 pluto: Fix dunf connection 2021-08-05 18:08:12 +03:00
stefan.raus bbb151f9f5 adi_project_xilinx.tcl: Set default value of ADI_USE_OOC_SYNTHESIS to 1 
In order to workaround optimization issues hit in Vivado 2020.2,
set ADI_USE_OOC_SYTHESIS variable by default to 1. This will build
projects in Out Of Context mode.
Projects can be build in Project Mode by exporting ADI_USE_OOC_SYTHESIS=n.
 2021-07-29 14:06:42 +03:00
stefan.raus 9d5de2fc21 Update Vivado version to 2020.2 
Update vivado version to 2020.2:
 - update default vivado version from 2020.1 to 2020.2
 - add conditions to apply specific contraints only in Out Of Context mode.
 - update DDR controler parameters for vcu118 and kcu105 dev boards
 2021-07-29 14:06:42 +03:00
Adrian Costina 907b750943 ad9083: Removed FIFO and increased DMAC transfer length 2021-07-28 12:45:20 +03:00
Iacob_Liviu 8343c03f5c adrv9371x: remove IOB attribute from rx and rx_os 2021-07-26 12:42:21 +01:00
David Winter 1158538753 adi_board: Fix ad_connect command tracing 
Signed-off-by: David Winter <david.winter@analog.com>
 2021-07-22 15:02:36 +03:00
David Winter 796af696da ad_fmclidar1_ebz: Remove invalid ad_connect invocations 
This commit removes two invalid ad_connect invocations, which weren't
caught in the original tests for commit cdda184007.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-07-22 15:02:25 +03:00
Laszlo Nagy a3e049ae03 scripts/adi_project_xilinx: Set number of parallel OOC jobs through environment variable 2021-07-13 10:09:08 +03:00
David Winter cdda184007 adi_board: Rewrite ad_connect to support all input permutations 
The goal of this commit is to make sure there isn't any significance to
the order in which parameters of ad_connect are specified.

As an example, previously you could only `ad_connect target VCC`, while
`ad_connect VCC target` would fail.

Note: This code intentionally ignores bd_{,intf_}ports, because
these can all be treated as bd_pins.

Signed-off-by: David Winter <david.winter@analog.com>
 2021-07-09 12:43:31 +03:00
stefan.raus 63ac142874 adrv9001:a10soc:system_qsys.tcl: set clock polarity to 0 
For fixing "Failed to reset the device and set SPI Config"
error, both clockPolarity and clockPhase should be disabled
or both enabled. By default both are unset.

Signed-off-by: Stefan Raus <stefan.raus@analog.com>
 2021-06-16 11:42:50 +03:00
Laszlo Nagy 75b965e87f ad9081_fmca_ebz/zcu102: Enable 204C modes 2021-06-10 09:53:43 +03:00
Laszlo Nagy 6637436c2e scripts/adi_board.tcl: Use div2 out clock from xcvr in case of GTH and 204C 2021-06-10 09:53:43 +03:00
Laszlo Nagy 27465ce9c0 ad9081_fmca_ebz/zcu102: Fix spaces 2021-06-10 09:53:43 +03:00
sergiu arpadi 7b7609d21a ad469x: Clean system_project.tcl 2021-06-03 15:41:58 +03:00
Laszlo Nagy d9bc014c98 adrv9001/zcu102: Enable independent Tx from Rx in CMOS mode 2021-05-26 15:44:45 +03:00
Laszlo Nagy 568bef4a38 adrv9001/a10soc: Initial version 
This project supports CMOS mode only.
 2021-05-26 15:44:45 +03:00
Owen McAree 5d008c3eca Correct constraints file pin mapping 2021-05-25 16:27:58 +03:00
Laszlo Nagy 0ad691a603 ad9081_fmca_ebz/zcu102: Differentiate parameters based on lane rate 2021-05-14 15:39:40 +03:00
Laszlo Nagy 8183599b51 ad9081_fmca_ebz/zcu102: Fix typo 2021-05-14 15:39:40 +03:00
Laszlo Nagy cf7f45ffcc ad9081_fmca_ebz: Fix for F=8 2021-05-14 15:39:40 +03:00
Laszlo Nagy 7b2ba41bdd ad9081_fmca_ebz/vcu118: Adjust QPLL params and diff swing 
This commit fixes the 16.5Gbps lane rate case where the link drops
after few seconds an initial successful link up happens.
A few seconds delayed calibration process can workaround this but with
having the differential drivers swing increased this is no longer
required.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy eba3409d78 ad9082_fmca_ebz: Use 9081 system_bd, updated comments 2021-05-14 15:39:40 +03:00
Laszlo Nagy 0d9e38bdbe ad9081_fmca_ebz: Update path to common block design 
Use absolute paths so ad9082 wrapper project can include the
system_bd.tcl instead of duplicating code.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 680d28476c ad9081_fmca_ebz: Add LANE_RATE param to all projects 
The block design expects a lane rate to be set in the system project.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy bd6ec360e2 ad9081_fmca_ebz/vcu118: Set XCVR params for 204C link 
Set XCVR parameter for 204C 24.75 Gbps with a  dynamic range of 10Gbps..24.75Gpbs

Organize XCVR params based on lane rate
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 693c002668 ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd: Add 204C support for XCVR 
Remove Xilinx PHY and simplify project
 2021-05-14 15:39:40 +03:00
Laszlo Nagy d92f925b06 ad9081_fmca_ebz: Disable XBAR from DAC TPL 2021-05-14 15:39:40 +03:00
Laszlo Nagy 77a5edaa83 scripts/adi_board.tcl: In 204C do not connect SYNC 
Take link mode parameter from util_adxcvr, check it against the axi_adxcvr.
 2021-05-14 15:39:40 +03:00
Laszlo Nagy 1db04a47b8 ad9083_evb: Update parameters to 10Gpbs lane rate 2021-04-19 13:21:34 +03:00
vladimirnesterov 8335e1bd9a sysid: Make sure gitbranch_string is always declared 
Parsing of not existed "gitbranch_string" fails the build process.
 2021-03-24 13:34:32 +02:00
Sergiu Arpadi 6a374ef457 ad469x/zed: Add multicycle path constraint 2021-03-22 13:05:05 +02:00
Sergiu Arpadi 40baa63f0f adrv2crr_fmcomms8: Fix system_top.v 2021-03-19 17:56:28 +02:00
Sergiu Arpadi a1773c661c adrv9009zu11eg_crr: Update spi 
Add two more CS signals to P25 connector
 2021-03-10 10:53:11 +02:00
sergiu arpadi 3dce87d09b ad9083: Add reference design for ad9083 eval board 2021-03-10 10:52:03 +02:00
Laszlo Nagy dcec4fe1b7 adrv9001/zc706: Fix spaces 2021-03-10 10:35:52 +02:00
Laszlo Nagy dc186645d8 adrv9001/zc706: Fix comments HPC to LPC 2021-03-10 10:35:52 +02:00
stefan.raus 4a772265a9 Update Quartus Prime version from 19.3.0 to 20.1.0 
adi_project_intel.tcl: Change quartus version to 20.1.0.
library: Set qsys version so that IP instances won't require a specific version.
 2021-03-08 11:29:33 +02:00
Laszlo Nagy 1099badaf4 ad9082_fmca_ebz:zc706: Initial version 2021-03-05 15:54:23 +02:00
Laszlo Nagy 2213527f29 ad9082_fmca_ebz:zcu102: Initial version 2021-03-05 15:54:23 +02:00