Add CMOS support for the interface for the following symbol modes on Xilinx devices:
A B C D E F G H
CSSI__1-lane 1 16/8 80(SDR)/160(DDR) 80 - SDR/DDR SDR/DDR->4/2(C=16), 2/1(C=8)
Columns description:
A - SSI Modes
B - Data Lanes Per Channel
C - Serialization factor Per data lane
D - Max data lane rate(MHz)
E - Max Clock rate (MHz)
F - Max Sample Rate for I/Q (MHz)
G - Data Type
H - DDS Rate
CSSI - CMOS Source Synchronous Interface
This commit changes the transfer length register to work in increments of
64 bytes and without offset. The true transfer length can now be
determined by multiplying the value of the transfer_length register with
64.
A value of zero is interpreted as a request for all available storage.
Additionally, this commit fixes an off by one issue that was discovered
during testing of the RX path.
Signed-off-by: David Winter <david.winter@analog.com>
Update vivado version to 2020.2:
- update default vivado version from 2020.1 to 2020.2
- add conditions to apply specific contraints only in Out Of Context mode.
- update DDR controler parameters for vcu118 and kcu105 dev boards
The width of the parameter `device_cfg_octets_per_multiframe` doesn't match the width in the submodules and corresponding slave module jesd204_tx, resulting in a warning generated during validation in Vivado. This patch increases the width of this parameter in axi_jesd204_tx.
Fix offset for pwms with different periods.
The previous version was using an offset scheme based on pwm counter_0.
By using a separate offset counter the user will not be constrained by
pwm_0 period in regards with the offset of other pulses. In this version
offset 0 is used to delay pwm 0 in regards to the offset counter.
The offset counter will start after the load_config signal is asserted
and all active pwm counters finish the previous cycle or by a software
reset.
The software reset should also be used when using external_sync.
* fixes DRC warning that the clocking configuration may result in data errors
* fixes ioserdes reset issue with synchronous de-assert in data clock domain
This commit adds a standalone TDD IP core based on the
existing up_tdd_cntrl module and the up_axi pcore <-> axi bridge.
Signed-off-by: David Winter <david.winter@analog.com>
If all channels are selected for read the values and ready signals from every
transceiver are combined. Each element merges his signals with the previous.
The first element of the chain must assume the previous channel is always ready.
This reverts commit 829e4155ca.
The first element of the read chain must assume there is no valid element
in front of it. For each element the ready signal of the transceiver should be
routed if the channel is selected either by channel number or broadcast.
When the current element is not selected it should forward the ready signal from
the previous element, however this is not the case for the first one.
Having a constant 1'b1 connected to the ready input of the first element
corrupts the first read of the first channel after a channel switch.
This change will break broadcast reads.
Adds a magic identification value of 0x54444443 at word address 0x3.
It is derived from the ASCII String "TDDC" interpreted as a big-endian
32-bit unsigned integer.
Signed-off-by: David Winter <david.winter@analog.com>
For GTH3/4 64b66b mode add a second clock that drives CLKUSR with a clock
that is 2x of the CLKUSR2 (lane rate/66),
CLKUSR = 2 x CLKUSR2
CLKUSR = lane rate / 33
This can be driven from the GT reference clock or second out clock div2.
This commit also:
- fix eyescan scale on GTY
- remove irrelevant parameters
alin724
Laszlo Nagy
stefan.raus
David Winter
Istvan Csomortani
Nick Pillitteri
Isaac T
AndreiGrozav
Iacob_Liviu
Josh Blum
Alin-Tudor Sferle