9093a8c428
library: Move ad_iobuf to the common library, as it's not Xilinx specific
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Updated all system_project and Makefiles
2020-11-02 16:13:35 +02:00
37254358dd
makefile: Regenerate make files
2020-10-20 12:51:10 +03:00
d8ab27b2af
sysid: Remove cstring init string
2020-09-30 19:12:24 +03:00
144fcc2965
adrv9009: Fix typo for number of samples calculation for observation channel
2020-09-25 11:58:58 +03:00
3241924d14
sysid_intel: Added sysid to intel projects
2020-09-11 15:46:06 +03:00
c8e0a1ec04
projects: adrv9009: intel: Update JESD204 LANE_RATE and REFCLK_FREQUENCY
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To match the Linux default setup.
Signed-off-by: Dragos Bogdan <dragos.bogdan@analog.com>
2020-09-09 14:15:37 +03:00
46b6bf8f8a
adrv9009/qsys: input pipline active for jesd204_rx and jesd204_rx_os
2020-09-09 14:15:37 +03:00
5a8f277253
adrv9009/s10soc: Add support for Stratix10 SOC
2020-09-09 14:15:37 +03:00
eb8e1142cd
adrv9009/intel: Fix the register address layout
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The reconfiguration interface for the Stratix10 XCVR has a different
address width. Prepare the register map layout of the project to support
this new architecture.
2020-09-09 14:15:37 +03:00
8818089015
a10soc: Reconfiguration interface address width improvement
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The reconfiguration interface's address width is different in various
architectures. Define the required address width in system_qsys.tcl.
2020-09-09 14:15:37 +03:00
a66029aef3
adrv9009/a10gx: Delete redundant timing constraints
2020-08-11 10:14:18 +03:00
02ada3bbf7
a10gx: Delete input/output delay definitions
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All input and output delays should be referenced to a virtual clock.
If the input and output delays reference base clocks or PLL clocks rather than
virtual clocks, the intra- and inter-clock transfer clock uncertainties,
determined by derive_clock_uncertainty, are incorrectly applied to the I/O ports.
See mnl_timequest_cookbook.pdf for more info.
2020-08-11 10:14:18 +03:00
71d500bdd4
adrv9009/intel: Use generic TPL cores
2020-05-26 16:22:30 +03:00
32eeedb660
makefile: Update makefiles
2020-05-07 08:41:49 +01:00
aa5fdf903e
Makefile: Update makefiles
2019-08-26 16:58:01 +03:00
78afe38a3f
adrv9009: Add decimation and interpolation filters
2019-08-20 16:24:47 +03:00
36a1767329
Add generic fir filters processes for RF projects
2019-08-20 16:24:47 +03:00
0680e44330
system_id: deployed ip
2019-08-06 16:53:11 +03:00
6e6f1347d7
project/scripts: Rename adi_project_alt.tcl to adi_project_intel.tcl
2019-06-29 06:53:51 +03:00
a589753d92
project/scripts: Rename adi_project.tcl to adi_project_xilinx.tcl
2019-06-29 06:53:51 +03:00
43725429ac
adi_project: Rename the process adi_project_xilinx to adi_project
2019-06-29 06:53:51 +03:00
79b6ba29ce
all: Rename altera to intel
2019-06-29 06:53:51 +03:00
424abe0c02
adrv9009: DMA should use $sys_dma_resetn
2019-06-13 10:59:43 +03:00
0e750bea42
adrv9009: Fix dma_clk tree
2019-06-11 18:13:06 +03:00
7960b00684
block_design: Update with new clock net variables
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Using the new clock net variables in all Xilinx block designs.
2019-06-11 18:13:06 +03:00
70b7d69ff8
whitespace: Delete all trailing white spaces
2019-06-07 10:20:15 +03:00
391ac468a7
adrv9009/common: Fix ad_xcvrcon proc call
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The process ad_xcvrcon has a device_clk attribute which can be used to
connect a custom device clock to the XCVR. Fix the proc call so we can
simplify the block design script.
2019-05-29 10:27:16 +03:00
c930395773
adrv9009:qsys: use bundled AXIS interface
2019-05-16 13:27:19 +03:00
d894c30c2d
Remove deprecated/unused parameters
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adrv9009
adrv9371x
arradio
daq2
daq3
fmcomms2
fmcomms5
2019-03-30 11:26:11 +02:00
3183fbf226
adrv9009: update adcfifo/dacfifo
2019-01-23 14:45:45 +02:00
0b66b39352
adrv9009/zc706: make SPI selection consistent
2018-12-21 17:32:48 +02:00
3d7a376f8b
Makefile: update makefiles
2018-12-21 17:32:48 +02:00
c9f1c92eaa
adrv9009: use generic TPL
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Make the block design parametrizable.
Limitations:
F = 1,2,4
2018-12-21 17:32:48 +02:00
47093775ae
adrv9009/zc706: top level cleanup
2018-12-21 17:32:48 +02:00
8adc285eab
adrv9009/zc706: fix location constraints
2018-12-21 17:32:48 +02:00
7a5a8c5340
Revert "adrv9009: Removed ZC706 based project"
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This reverts commit 7e7f75c0270bb6793bedb339f62b67bab9d77a6e.
2018-12-21 17:32:48 +02:00
e09f3290ff
adrv9009: Move intel project to upack2/cpack2
2018-12-03 12:23:24 +00:00
2462f8e50f
adrv9009: Use new pack/unpack infrastructure
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Use the new util_cpack2 and util_upack2 cores. They have lower utilization
that the old util_cpack and util_upack cores.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2018-11-28 11:33:11 +02:00
401395cdd1
adrv9009: A10GX: Initial commit
2018-11-27 15:31:21 +02:00
e4048c7b04
adrv9009: A10SOC: Add second observation channel
2018-11-27 15:31:21 +02:00
f12bd3d246
adrv9009: A10SOC: Initial commit
2018-11-27 15:31:21 +02:00
559e00fd75
adrv9009/zcu102: Increase DAC buffer depth to 18Mb
2018-10-11 16:57:30 +03:00
1931d65b7a
adrv9009/zcu102: Update initial configuration for GT clock output control
2018-10-04 14:37:02 +03:00
4ce153e6e1
all/system_top.v: loopback gpio lines
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Create loopback on unused GPIO lines since Linux may rely on it.
2018-10-04 14:19:37 +03:00
31318cf311
all/system_top.v: drive unused gpio inputs with zero
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The loopback on the unused gpio inputs consumes routing resources
while does not gives any value for the software.
Connect these lines to zero instead.
2018-08-10 17:00:11 +03:00
05789e8978
adrv9009/adrv9371x/fmcomms2:Drop usage of ad_iobuf on non-bidirectional IOs
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Some projects use the ad_iobuf on IOs that are not bidirectional
producing synthesis warnings.
The change fixes warnings like:
[Synth 8-6104] Input port 'gpio_bd_i' has an internal driver
[Synth 8-6104] Input port 'gpio_status' has an internal driver
2018-08-10 17:00:11 +03:00
ebae8bf8c1
Remove interrupts from system_top for all xilinx projects
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- remove interrupts from system_top
- for all suported carriers:
- remove all interrupt bd pins
- connect to GND all initial unconnected interrupt pins
- update ad_cpu_interrupt procedure to disconnect a interrupt from GND
before connectiong it to another pin.
2018-08-10 10:10:58 +03:00
41e717ec2c
adrv9009: Added option for enabling the second observation channel
2018-06-29 11:10:39 +03:00
e982232d75
adrv9009: Increased DMA clock frequency to ~333 MHz, by enabling AXI SLICES for DMAs
2018-06-12 23:53:56 +03:00
f3ac5d3ad3
adrv9009: Increase all DMAs MAX_BYTES_PER_BURST to 256
2018-06-12 23:53:56 +03:00
Adrian Costina
Istvan Csomortani
Sergiu Arpadi
Dragos Bogdan
AndreiGrozav
Laszlo Nagy
Lars-Peter Clausen