Adrian Costina
|
780455d68c
|
Makefile: Updated makefiles. Added makefiles for altera
|
2015-04-09 17:57:06 +03:00 |
Rejeesh Kutty
|
5f8e9a74ea
|
makefile: updated
|
2015-04-07 16:32:01 -04:00 |
|
Adrian Costina
|
f79a152958
|
Makefiles: updated all makefiles adding clean functionality
|
2015-04-03 11:57:54 +03:00 |
|
Rejeesh Kutty
|
79a07e737d
|
makefile: added
|
2015-04-01 16:28:56 -04:00 |
|
Rejeesh Kutty
|
b3c666cf0d
|
makefile: added
|
2015-04-01 16:28:55 -04:00 |
Istvan Csomortani
|
75d2c7e93e
|
daq1_zc706: Update project to the new framework
|
2015-03-24 12:45:24 +02:00 |
|
Istvan Csomortani
|
68ac015825
|
daq1_fmcl: Fix GT lane number definitions
Update which fix issues caused by GT lane number parameters change. (commit f8e7796592)
|
2014-11-24 18:23:33 +02:00 |
|
Istvan Csomortani
|
0ecfc14e95
|
daq1_fmc: Update interrupts.
|
2014-11-24 18:23:32 +02:00 |
|
Istvan Csomortani
|
9b104f1657
|
daq1_fmc: Get rid of the concat module inside the block design.
xl_concat just causing troubles, no need to use it, if not justified.
|
2014-11-24 18:23:30 +02:00 |
|
Istvan Csomortani
|
17675863e0
|
all_projects: Fix the interrupt connections to preserve IRQ layout
|
2014-10-22 11:48:08 +03:00 |
|
Rejeesh Kutty
|
577441bd0c
|
daq1: clean up dma interfaces
|
2014-09-23 14:23:41 -04:00 |
|
Istvan Csomortani
|
dd7bac41c1
|
daq1 : Update project to 2014.2
- Cores are upadted
- Concat module does not swap output anymore
- Clock signal name ps7_clk_* changed to clk_fpga_*
|
2014-09-22 17:33:50 +03:00 |
|
Istvan Csomortani
|
751bdd6cfc
|
daq1: Update the constraint file
- tx_ref_clk and rx_sysref need to be differential
- cosmetic changes
|
2014-09-19 18:22:57 +03:00 |
|
Istvan Csomortani
|
a91f4bb6b9
|
daq1: General updates
- Add additional GT setups
- Use channel PLL instead of quad PLL
- Add additional ILA probes for debug
|
2014-09-13 00:23:11 +03:00 |
|
Istvan Csomortani
|
ee752ec08a
|
daq1: Initial commit
|
2014-09-01 18:34:31 +03:00 |