f415b4f973
axi_ad5766: Delete unused interface definition
2017-06-20 11:55:10 +01:00
871855c9ec
axi_logic_analyzer: Fix delayed trigger assertion condition
2017-06-19 10:58:22 +03:00
d840baee28
util_clkdiv: Register output port as a clock ( #33 )
...
If the output pin is not defined as a clock, some of the Vivado IPI
propagation TCL will error out.
Signed-off-by: Matt Fornero <matt.fornero@mathworks.com>
2017-06-19 07:52:43 +01:00
dc94dd3ea7
jesd204- apply constraints after top
2017-06-16 15:30:18 -04:00
513f6ae18a
adi_ip.tcl- general rule- order independent constraints
2017-06-16 13:51:35 -04:00
9e2d55ed07
adi_ip_alt: allow composition only parameter settings
2017-06-15 11:36:39 -04:00
9464f342cf
avl_adxcvr: remove arria v support
2017-06-15 11:36:14 -04:00
2fc5d08c0b
axi_gpreg: Fixed constraints
2017-06-13 14:04:43 +03:00
173837f5b2
altera- altera ip interfaces has no consistency
2017-06-09 16:21:44 -04:00
227bd3edfe
alt_ifconv-- qsys workaround
2017-06-09 16:17:34 -04:00
034aa7c1ee
altera 16.1- recommends using fpll for dedicated low skew clock routing
2017-06-08 10:50:52 -04:00
3f2c885189
axi_logic_analyzer: Update triggering delay mechanism
2017-06-08 12:01:49 +03:00
256a685004
axi_adc_trigger: Update triggering delay mechanism
2017-06-08 12:00:27 +03:00
7554887982
avl_dacfifo: Fix timing violation
...
+ Transfer avl_last_beats into dac clock domain
+ Update constraint file
2017-06-07 11:02:44 +01:00
dd48929327
hdlmake.pl - updates
2017-06-06 12:25:35 -04:00
41d305b6b6
up_clock_mon- name changes
2017-06-06 11:36:18 -04:00
4cc5052b3a
util_fir_int: Fix valid assignment
2017-06-06 17:53:41 +03:00
ac55e850a9
axi_logic_analyzer: Added trigger delay register, renamed fifo depth register
2017-06-06 15:37:00 +03:00
3148c85f73
axi_adc_trigger: Added trigger delay register, renamed fifo depth register
2017-06-06 15:35:59 +03:00
95c446a41d
adi_ip- initialize xdc list when ip is created
2017-06-01 15:49:18 -04:00
6a437472f2
jesd204-sub-ip- no top files
2017-06-01 15:48:48 -04:00
50cdb6db67
Merge branch 'jesd204' into dev
2017-05-31 20:44:32 +03:00
cb4e8f66ef
axi_ad9963: Delete unused source from *_ip.tcl
2017-05-31 18:27:47 +03:00
84b2ad51e2
license: Add some clarification to the header license
2017-05-31 18:18:56 +03:00
3a4a91b6f1
util_extract: Estetic changes
2017-05-31 11:27:32 +03:00
7aa1673238
util_extract: Update parameter names
2017-05-29 16:04:56 +03:00
85ebd3ca01
license: Update license terms in hdl source files
...
Fix a few gramatical error, fix the path of the top level license
files.
2017-05-29 09:55:41 +03:00
aaae350b3d
alt_serdes- 16.1 updates
2017-05-26 11:00:07 -04:00
25e42c49d6
library: move alt cores to common
2017-05-26 10:51:25 -04:00
ff037c0286
altera 16.1 ip changes
2017-05-26 10:48:00 -04:00
097924b95d
altera 16.1 ip changes
2017-05-26 10:46:28 -04:00
10898d6618
constraints: Split the regmap CDC constraint into separate file
2017-05-25 15:12:16 +03:00
cb8d6830f5
avl_dacfifo: Update constraints
2017-05-25 15:12:16 +03:00
3ee7ed7375
avl_dacfifo: Cosmetic changes
2017-05-25 15:12:15 +03:00
154e936a4b
avl_dacfifo: Fix issues with avl_dacfifo_wr
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+ fix issues with the last partial avalon transfer.
+ fix reset related problems
2017-05-25 15:12:15 +03:00
e34e87e7f8
avl_dacfifo: Add support for partial avalon transfers
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By adding support for partial avalon transfers (data width < bus width),
valid data set size (DMA transfer length) will be dependent on the DMA bus
width only.
2017-05-25 15:12:15 +03:00
a993eefe57
avl_dacfifo: Grey coder/decoder integration
2017-05-25 15:12:14 +03:00
0bf6a37bd0
common: Add grey coder and decoder modules
2017-05-25 15:12:14 +03:00
14a058195d
avl_dacfifo: Add avl_dacfifo_byteenable_coder
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Define and integrate avl_dacfifo_byteenabke_coder module,
which generates the byteenable signal for the avalon interface.
2017-05-25 15:12:14 +03:00
81fa65cd51
avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
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+ avl_write_transfer_done_s is a redundant net
+ specify the net state explicitly on if statements
+ to define the edge of avl_mem_fetch_wr_address signal,
its register and its second sync register should be used
2017-05-25 15:12:13 +03:00
398619d866
avl_dacfifo: Add support for MEM_RATIO 32
2017-05-25 15:12:13 +03:00
a1539a62b7
avl_dacfifo: Integrate util_delay into dac_xfer_out path
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The ad_mem_asym memory read interface has a 3 clock cycle delay, from the
moment of the address change until a valid data arrives on the bus;
because the dac_xfer_out is going to validate the outgoing samples (in conjunction
with the DAC VALID, which is free a running signal), this module will compensate
this delay, to prevent duplicated samples in the beginning of the
transaction.
2017-05-25 15:12:13 +03:00
6d52034abb
avl_dacfifo: dma_ready was muxed incorrectly
2017-05-25 15:12:12 +03:00
da68705fee
avl_dacfifo: Fix the avalon address switch
2017-05-25 15:12:12 +03:00
04f397f688
avl_dacfifo: Fix a few control signals
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+ avl_last_transfer depends on the avl_xfer_req state
+ avl_xfer_req will be asserted after the last avalon write
transfer
2017-05-25 15:12:12 +03:00
8f9cadb017
avl_dacfifo: Fix the avl_write generation
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The asymetric memory has a 3 clock cycle delay on its read
interface, therefor the minimum distance between two consecutive
avalon write should be 3.
2017-05-25 15:12:11 +03:00
0f1e51ac98
avl_dacfifo: Fix alv_mem_readen generation
2017-05-25 15:12:11 +03:00
f456ebc6f0
avl_dacfifo: Few cosmetic changes on avl_dacfifo_wr
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+ all net names should have a *_s postfix
+ avl_burstcount is a constant 1, no need for an additional
register for it
+ all CDC should have two synchronization register, add
avl_last_beat_req_m2
2017-05-25 15:12:11 +03:00
6ea87d094e
util_delay: Initial commit
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Generic module to introduce a fix N cycle delay into a datapath.
2017-05-25 15:12:10 +03:00
9a6dc36289
avl_dacfifo: Fix indentation for acl_dacfifo.v
2017-05-25 15:12:10 +03:00
Istvan Csomortani
Adrian Costina
Matthew Fornero
Rejeesh Kutty
AndreiGrozav