pluto_hdl_adi

Commit Graph

Author	SHA1	Message	Date
Lars-Peter Clausen	55daa786fa	axi_adcfifo: Add missing constraints Add missing timing exceptions on paths between the DMA and DDR clock domains. All these paths are properly synchronized using CDC in the HDL, but are missing timing exceptions in the XDC file. This can lead to timing errors when building a design using the axi_adc_fifo. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>	2017-09-13 19:52:48 +02:00
Istvan Csomortani	3cbbc771a8	axi_adcfifo: Move IP to library/xilinx	2016-09-15 11:36:47 +03:00

Author

SHA1

Message

Date

Lars-Peter Clausen

55daa786fa

axi_adcfifo: Add missing constraints

Add missing timing exceptions on paths between the DMA and DDR clock
domains. All these paths are properly synchronized using CDC in the HDL,
but are missing timing exceptions in the XDC file. This can lead to timing
errors when building a design using the axi_adc_fifo.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>

2017-09-13 19:52:48 +02:00

Istvan Csomortani

3cbbc771a8

axi_adcfifo: Move IP to library/xilinx

2016-09-15 11:36:47 +03:00

2 Commits (f3daf0dacba8f15fe49616fedd3c145509cec7cc)