Rejeesh Kutty
|
e38813fa9f
|
fifo- monitor status signals
|
2014-06-25 12:15:13 -04:00 |
|
Rejeesh Kutty
|
57bb3705f2
|
zc706-plddr3: read changes to lower dma clock
|
2014-06-25 09:20:58 -04:00 |
|
Rejeesh Kutty
|
c789dce77e
|
ad9625/zc706: added pl ddr3 fifo changes
|
2014-05-29 12:59:29 -04:00 |
|
Rejeesh Kutty
|
56ddce1e8c
|
dmac: create fifo interface to avoid being treated as axi control stream
|
2014-05-27 10:25:14 -04:00 |
|
Rejeesh Kutty
|
f73819f4d4
|
zc706: pl ddr3 initial checkin
|
2014-05-13 16:19:53 -04:00 |
|
Rejeesh Kutty
|
fbfd658f0d
|
zc706: added pl ddr3 mig
|
2014-04-09 15:58:12 -04:00 |
Istvan Csomortani
|
f9a67371c0
|
Zynq Base System: Reset is synchronized to lowest system clock
System reset (sys_100m_reset) is synchronized to lowest system
clock (FCLK0), via a Processor System Reset module
|
2014-03-26 17:58:14 +02:00 |
|
Rejeesh Kutty
|
dc44703cf1
|
zynq/non-zynq: identical signal names and instances
|
2014-03-17 17:02:03 -04:00 |
|
Rejeesh Kutty
|
a6da4ca01c
|
zynq/non-zynq merge variables
|
2014-03-17 16:39:52 -04:00 |
|
Rejeesh Kutty
|
f3ae57a53e
|
global clock and reset names
|
2014-03-11 09:57:59 -04:00 |
|
Rejeesh Kutty
|
ddac1a8834
|
added common board files
|
2014-02-28 21:17:01 -05:00 |