Rejeesh Kutty
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b3ce821311
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change pl ddr clock to 1G
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2017-05-01 09:35:10 -04:00 |
|
Rejeesh Kutty
|
cc6bf53d98
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adrv9371x/a10soc- altera reset synchronizer false path?
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2017-03-23 09:46:40 -04:00 |
|
Rejeesh Kutty
|
3fa9a30f0e
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a10soc/plddr4- lower mem clk to meet timing
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2017-03-06 14:12:25 -05:00 |
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Rejeesh Kutty
|
bc6a09c828
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adrv9371x/a10soc- dacfifo added
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2017-03-01 15:35:04 -05:00 |
Adrian Costina
|
ce3b6a2d3f
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adrv9371x: Updated constraints for altera projects
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2016-11-04 18:20:46 +02:00 |
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Adrian Costina
|
521c41ce32
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adrv9371x: Updated a10soc project. Common design differentiates between nios and a10soc carrier
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2016-09-08 11:44:45 +03:00 |
|
Rejeesh Kutty
|
3351ff607e
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adrv9371x- need to investigate merge with avalon
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2016-06-02 16:22:53 -04:00 |
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Rejeesh Kutty
|
0d1c4d232e
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a10soc- updates-1
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2016-05-20 16:14:57 -04:00 |
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Rejeesh Kutty
|
f92e8509bb
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adrv9371x- added
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2016-05-20 11:46:25 -04:00 |