Commit Graph

809 Commits (f079b2193a55dafe2ee1147470e36a5a84ff8b8a)

Author SHA1 Message Date
Lars-Peter Clausen f079b2193a axi_dmac: Add support for auto-detecting asynchronous clock configuration
Add support for querying the clock domains of the clock pins for the
axi_dmac controller. This allows the core to automatically figure out
whether its different parts run in different clock domains or not and setup
the configuration parameters accordingly.

Being able to auto-detect those configuration parameters makes the core
easier to use and also avoids accidental misconfiguration.

It is still possible to automatically overwrite the configuration
parameters by hand if necessary.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:15 +02:00
Lars-Peter Clausen 19f7d8500c adi_ip.tcl: Add support for adding bd files to a core
bd files can be used to automate certain tasks in IP integrator when the
core is instantiated. Add a helper command for adding such files to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:14 +02:00
Lars-Peter Clausen 39320ef48b axi_dmac: Fix source pause signal
For the source controller use the pause signal that has been properly
transferred to the source clock domain rather than the pause signal from
the request clock domain.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:13 +02:00
Lars-Peter Clausen 91bb54467b axi_dmac: Generate per core instance constraint file
When having multiple DMA cores sharing the same constraint file Vivado
seems to apply the constraints from the first core to all the other cores
when re-running synthesis and implementation from within the Vivado GUI.

This causes wrong timing constraints if the DMA cores have different
configurations. To avoid this issue use a TTCL template that generates a
custom constraint file for each DMA core instance.

This also allows us to drop the asynchronous clock detection hack from the
constraint file and move it to the template and only generate the CDC
constraints if the clock domains are asynchronous.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:12 +02:00
Lars-Peter Clausen 0f5f21eec2 adi_ip.tcl: Add helper function to add TTCL files to a core
Add a helper function which allows to add TTCL templates files to a core.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-18 15:27:10 +02:00
Adrian Costina 46808c4c41 util_wfifo: Changed some reset for several registers from asynchronous to synchronous for better integration with the FIFO 2015-09-16 18:55:47 +03:00
Adrian Costina 6804f3377a axi_ad9643: Updated core with latest constraints 2015-09-16 15:49:13 +03:00
Adrian Costina 5347c058df axi_ad9122: Updated core with latest constraints 2015-09-16 15:48:33 +03:00
Adrian Costina 884f45c81d common library: Registered dc_filter and iq_correction coefficients 2015-09-16 14:24:18 +03:00
Adrian Costina 67ffeb18e8 axi_ad9739a: Updated core with latest constraints 2015-09-11 14:04:33 +03:00
Adrian Costina e33403816c axi_ad9265: Updated core with latest constraints 2015-09-11 11:26:28 +03:00
Istvan Csomortani 5bc16159fa ad_tdd_sync: The resync will reset all the control lines 2015-09-10 11:28:36 +03:00
Istvan Csomortani a679251d7d Makefiles: Update Make 2015-09-09 17:13:19 +03:00
Istvan Csomortani 85ffc25ec5 ad_tdd_sync: Update the synchronization logic
The synchronization interface is a single bidirectional line. Output for Master, input for Slave.
The sync_period value is relative to frame length and the digital interface clock. The actual synchronization
period will be: sync_period * frame_length * fb_clock_cycle
2015-09-09 12:31:58 +03:00
Istvan Csomortani 5a566b9e5d ad_tdd_control: Add delay compensation for the control lines 2015-09-09 12:24:26 +03:00
Istvan Csomortani 6acb350ee5 axi_dmac: Update for axi_dmac_constr.xdc
Parameter called 'processing_order' default value is 'late'. No need to specify it at process call.
2015-09-09 12:08:35 +03:00
Rejeesh Kutty 381ffd43c1 gtlb- remove pn test-reset 2015-09-08 13:52:33 -04:00
Rejeesh Kutty 9bef9742b7 jesd_gt- cosmetic changes 2015-09-03 16:16:24 -04:00
Rejeesh Kutty 84ced344d9 gtlb- up-sync make w1c 2015-09-03 16:16:22 -04:00
Lars-Peter Clausen e0b5044aa3 axi_dmac: Disable dummy AXI ports for Xilinx IPI
The memory mapped AXI interfaces for the AXI-DMAC are uni-directional.
Which means they are either write-only or read-only. Unfortunately the
Altera tools can't handle this, so we had to add dummy signals for the
other direction.

The Xilinx tools on the other hand handle uni-directional AXI interfaces
and in fact IPI can do a better job and use less resources when creating
the AXI interconnects when it knows that the interface is uni-directional.
So always disable the dummy ports for the IPI package.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
2015-09-01 11:29:36 +02:00
Rejeesh Kutty 2a09257f38 pzslb- updates - wip 2015-08-31 15:41:28 -04:00
Rejeesh Kutty c1b01517f8 util_gtlb: added 2015-08-31 15:41:22 -04:00
Rejeesh Kutty 1e5afdd535 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 6cf7eb5ad4 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 4554eb03b0 axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 704385a8dc axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty a33c08725b axi_hdmi_tx- altera ip changes 2015-08-28 13:48:33 -04:00
Rejeesh Kutty 1cd3435147 up_delay_cntrl- cosmetics 2015-08-28 13:16:18 -04:00
Rejeesh Kutty 8fddf983d2 up_hdmi_tx- common/generic instance names 2015-08-27 13:17:06 -04:00
Rejeesh Kutty 88f806f584 ad9361- alt io matching 2015-08-27 11:55:24 -04:00
Rejeesh Kutty 74e72021f7 ad9361- ensm through dev-if 2015-08-27 11:41:53 -04:00
Rejeesh Kutty 664ef017bb ad9361- ensm through dev-if 2015-08-27 11:41:52 -04:00
Rejeesh Kutty 29b0ec0378 ad9361- ensm through dev-if 2015-08-27 11:41:51 -04:00
Rejeesh Kutty d82d37c23f ad9361- ensm through dev-if 2015-08-27 11:41:49 -04:00
Rejeesh Kutty 2259b6cbf7 ad9361- ensm through dev-if 2015-08-27 11:41:48 -04:00
Rejeesh Kutty 20ee10ea46 common/ad_lvds_out- add single ended 2015-08-27 11:41:47 -04:00
Rejeesh Kutty c56b534ec0 dacfifo- remove interfaces 2015-08-27 11:18:00 -04:00
Rejeesh Kutty ba64de228e ip-constr- register name changes 2015-08-27 11:18:00 -04:00
Rejeesh Kutty f3410a7db1 xpack- remove useless interfaces 2015-08-26 14:12:14 -04:00
Rejeesh Kutty b0d22d323a ad9361- axi-clock definitions 2015-08-26 14:11:43 -04:00
Rejeesh Kutty 4655af7bf6 2015.2 updates 2015-08-26 11:33:44 -04:00
Rejeesh Kutty 18f688514b 2015.2 updates 2015-08-26 11:33:37 -04:00
Rejeesh Kutty 7780b3a3a2 2015.2 updates 2015-08-26 11:33:27 -04:00
Istvan Csomortani 7b858bc5ad Revert commit 6b99ce
Revert 6b99ce2482
2015-08-26 13:48:28 +03:00
Istvan Csomortani 386cc74ab4 util_axis_fifo: Fix port names at util_axis_fifo_ip.tcl
Fix port names at the 'port_maps' attribute of the adi_add_bus process call.
2015-08-25 09:41:34 +03:00
Istvan Csomortani c2ea667a01 library/IPI: Set ASSOCIATED_RESET parameter for AXI interface
For some reason, if a core has an AXI and an AXI Stream interface too, the tool sets the AXI interface's ASSOCIATED_RESET parameter to the AXI Stream interface's reset.
This cause an unconnected AXI reset port in the block design. This 'set_property' command intended to overwrite this automated setup.
2015-08-25 09:36:42 +03:00
Istvan Csomortani 0c3f110bff library: Fix broken parameters
Fix the broken parameters for the following IP cores: axi_i2s_adi, axi_spdif_tx, util_cpack. Make additional name changes on the local parameters.
2015-08-25 09:19:47 +03:00
Istvan Csomortani da315eb6c0 library: 2015.2 updates
IPI bus interface names have changed in this new release.
2015-08-25 09:13:24 +03:00
Rejeesh Kutty 0077117f94 dac/adc- make common instances 2015-08-21 14:41:39 -04:00
Rejeesh Kutty c45d39df51 dac/adc- make common instances 2015-08-21 14:41:35 -04:00