Rejeesh Kutty
|
69ee410d3d
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fmcomms2/zc706pr- bypass pr as default
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2016-11-21 09:45:10 -05:00 |
Rejeesh Kutty
|
1cbea90bac
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altera - a10gx bank swap
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2016-11-01 12:41:25 -04:00 |
Rejeesh Kutty
|
1e0fed82f7
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alt_serdes- a10 ddio fixes
|
2016-11-01 12:41:25 -04:00 |
Rejeesh Kutty
|
671a547c2b
|
hdlmake- updates
|
2016-11-01 12:41:25 -04:00 |
Rejeesh Kutty
|
7b958fed87
|
hdlmake- updates
|
2016-10-21 13:59:43 -04:00 |
AndreiGrozav
|
17cfdd6be9
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fmcomms2/a10gx: Update Makefile and qsys script
|
2016-10-18 12:42:14 +03:00 |
Rejeesh Kutty
|
cb97bc500a
|
hdlmake updates
|
2016-10-17 16:29:57 -04:00 |
Rejeesh Kutty
|
905e29eb01
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hdlmake- altera
|
2016-10-10 12:55:55 -04:00 |
Rejeesh Kutty
|
8e1034946f
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fmcomms2/zcu102- 2016.2 updates
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2016-09-30 11:55:10 -04:00 |
Istvan Csomortani
|
f1e787f86b
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fmcomms2: TDD control is enabled by default
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2016-09-16 14:45:39 +03:00 |
Istvan Csomortani
|
16ee1336c3
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Makefile: Update make files
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2016-09-15 11:41:06 +03:00 |
Rejeesh Kutty
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f697490de6
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hdlmake- updates
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2016-08-19 15:59:41 -04:00 |
Adrian Costina
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0b0aa8e6c0
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Makefile: Add MMU option to altera makefiles
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2016-08-11 17:46:54 +03:00 |
Istvan Csomortani
|
0cd608a7e2
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lib_refactoring: Update Make files
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2016-08-08 16:38:38 +03:00 |
Istvan Csomortani
|
df36902713
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lib_refactoring: Fix path of the IO macros
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2016-08-08 15:07:19 +03:00 |
Adrian Costina
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d60bce654c
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Makefiles: Updated Makefiles so they run correctly with gnuwin32 tools
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2016-08-05 15:16:04 +03:00 |
Rejeesh Kutty
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e42b4ea378
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hdlmake- updates
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2016-08-04 13:28:25 -04:00 |
Istvan Csomortani
|
7ca8e10004
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make: Update Make files
|
2016-08-01 14:24:48 +03:00 |
Istvan Csomortani
|
af4c43b6e1
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hdl-vivado-2016.2: Update fmcomms2 and pzsdr base design
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2016-08-01 13:49:12 +03:00 |
Rejeesh Kutty
|
39a5534e00
|
hdlmake- updates
|
2016-07-21 16:10:38 -04:00 |
AndreiGrozav
|
12abe2b6b9
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fmcomms2: Makefile update
|
2016-07-12 09:39:24 +03:00 |
AndreiGrozav
|
283bf9ad75
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fmcomms2_a10GX: Add fmcomms2 on a10gx
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2016-07-11 18:37:18 +03:00 |
AndreiGrozav
|
e9fe752b7a
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fmcomms2_qsys.tcl: Add fmcomms2 block design script for Altera
|
2016-07-11 18:34:21 +03:00 |
Rejeesh Kutty
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48762519b5
|
make updates
|
2016-07-06 15:02:00 -04:00 |
Rejeesh Kutty
|
67c948e821
|
fmcomms2/a10soc-- bad board design
|
2016-06-14 12:29:36 -04:00 |
Rejeesh Kutty
|
eaf4d4a19d
|
makefile updates
|
2016-06-10 14:26:14 -04:00 |
Rejeesh Kutty
|
09520709b0
|
make updates
|
2016-05-20 12:35:45 -04:00 |
Rejeesh Kutty
|
e1350018da
|
zcu102- updates
|
2016-05-10 15:40:41 -04:00 |
Rejeesh Kutty
|
a6411dbd63
|
zcu102- added
|
2016-05-10 15:40:41 -04:00 |
AndreiGrozav
|
8d72b645ae
|
fmcomms2/common: Remove ila_tdd block
|
2016-05-09 10:28:10 +03:00 |
Rejeesh Kutty
|
ddfaff2cf5
|
fmcomms2/a10soc: compile version
|
2016-05-04 13:42:12 -04:00 |
Rejeesh Kutty
|
f4e5965936
|
fmcomms2/a10soc: ip updates
|
2016-05-04 13:42:12 -04:00 |
Rejeesh Kutty
|
385ed31a45
|
make files update
|
2016-04-29 10:17:35 -04:00 |
Rejeesh Kutty
|
61b531b1c1
|
a10soc device update
|
2016-04-29 10:17:35 -04:00 |
Rejeesh Kutty
|
e790e4c3ae
|
a10soc- complete qsys
|
2016-04-25 12:56:19 -04:00 |
Rejeesh Kutty
|
bfa6fe2a40
|
a10soc- updates
|
2016-04-25 11:23:16 -04:00 |
Rejeesh Kutty
|
28159aeec9
|
a10soc- updates
|
2016-04-25 11:11:46 -04:00 |
Rejeesh Kutty
|
0a3967b886
|
a10soc- updates
|
2016-04-25 10:53:26 -04:00 |
Rejeesh Kutty
|
d36d1263c5
|
a10soc- updates
|
2016-04-25 10:50:09 -04:00 |
Rejeesh Kutty
|
2a5f31d26b
|
fmcomms2/a10soc- copy
|
2016-04-22 15:15:44 -04:00 |
AndreiGrozav
|
679d471d75
|
Merge branch 'hdl_2016_r1' into dev
hdl_2016_r1 contains IP core upgrades to Vivado 2015.4.2 and hdmi_tx improvements.
|
2016-04-19 18:05:50 +03:00 |
Rejeesh Kutty
|
3006c5a223
|
make updates
|
2016-04-11 16:14:59 -04:00 |
AndreiGrozav
|
21208ca208
|
Makefiles: Update Makefiles
|
2016-03-31 12:37:47 +03:00 |
AndreiGrozav
|
995debedce
|
fmcomms2: Update common design to 2015.4
|
2016-03-18 15:26:52 +02:00 |
AndreiGrozav
|
ceea7f25b2
|
fmcomms2: Updated common design to 2015.4
|
2016-03-15 15:23:20 +02:00 |
Istvan Csomortani
|
e381d5170c
|
util_tdd_sync: Update the synchronization interface
Simplify the synchronization interface, there is one signal line between the synchronization module and transceiver core.
|
2016-02-12 14:27:37 +02:00 |
Istvan Csomortani
|
c051a578e5
|
fmcomms2: Delete unnecessary clock definition
The two clocks, rx_clk and ad9361_clk, are the same.
|
2015-11-20 19:35:37 +02:00 |
Istvan Csomortani
|
2345d29663
|
fmcomms2: Update make files
|
2015-11-11 11:15:45 +02:00 |
Istvan Csomortani
|
a936ad607f
|
fmcomms2/zc706: Delete unused files from file list
|
2015-11-11 11:14:58 +02:00 |
Istvan Csomortani
|
c7e86528d6
|
fmcomms2/zc706: Cosmetic changes on constraints file
|
2015-11-11 11:14:16 +02:00 |